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x86-64 is a 64-bit superset of the X86 Instruction Set Architecture . The x86-64 instruction set natively supports Intel 's x86 and was designed by Advanced Micro Devices (AMD), who have since renamed it '''AMD64'''. This architecture has been cloned by Intel under the name '''Intel 64''' (formerly known as Yamhill, Clackamas Technology (CT), IA-32e, and EM64T). Extending the World's Most Popular Processor Architecture This leads to the common use of the names ''x86-64'' or '''x64''' as more vendor-neutral terms to collectively refer to the two nearly identical implementations.

x86-64 is not the same as IA-64 , the underlying Instruction Set architecture of Intel's Itanium branded processors.


AMD64


The AMD64 instruction set is currently implemented in AMD's Athlon 64 , Athlon 64 FX , Athlon 64 X2 , Turion 64 , Turion 64 X2 , Opteron and later Sempron processors.


History of AMD64


The first AMD64-based processor, the Opteron, was released in April 2003.


Architectural features

The primary defining characteristic of AMD64 is its support for 64-bit general purpose registers, 64-bit integer arithmetic and logical operations, and 64-bit virtual addresses. The designers took the opportunity to make other improvements as well. The most significant changes include:

  • Full support for 64-bit integers: All general-purpose registers (GPRs) are expanded from 32 bits to 64 bits, and all arithmetic and logical operations, memory-to-register and register-to-memory operations, etc., are now directly supported for 64-bit integers. Pushes and pops on the stack are always in eight-byte strides, and pointers are eight bytes wide.


  • '''Additional to 16. It is therefore possible to keep more local variables in registers rather than on the stack, and to let registers hold frequently accessed constants; arguments for small and fast subroutines may also be passed in registers to a greater extent. However, more registers also involves more saving and restoring of register contents, and AMD64 still has fewer registers than many common RISC processors (which typically have 32–64 registers) or VLIW -like machines such as the IA-64 (which has 128 registers).


  • Additional XMM (SSE) registers: Similarly, the number of 128-bit XMM registers (used for Streaming SIMD instructions) is also increased from 8 to 16.


  • Larger virtual address space: Current processor models implementing the AMD64 architecture can address up to 256  Tebibyte s of virtual address space (248 bytes). This limit can be raised in future implementations to 16  Exbibyte s (264 bytes). This is compared to just 4  Gibibyte s for 32-bit x86. This means that very large files can be operated on by mapping the entire file into the process' address space (which is generally faster than working with file read/write calls), rather than having to map regions of the file into and out of the address space.


  • Larger physical address space: Current implementations of the AMD64 architecture can address up to 1  Tebibyte of RAM (240 bytes); the architecture permits extending this to 4  Pebibyte s (252 bytes) in the future (limited by the page table entry format). In Legacy Mode , Physical Address Extension (PAE) is supported, as it is on most current 32-bit x86 processors, allowing access to a maximum of 64 gibibytes.


  • Instruction pointer relative data access: Instructions can now reference data relative to the instruction pointer (RIP register). This makes Position Independent Code , as is often used in shared libraries and code loaded at run time, more efficient.


  • SSE instructions: The original AMD64 architecture adopted Intel's SSE and SSE2 as core instructions. SSE3 instructions were added in April 2005. SSE2 replaces the X87 instruction set's IEEE 80-bit Precision , with the choice of either IEEE 32-bit or 64-bit floating-point mathematics. This provides floating-point operations compatible with many other modern CPUs. The SSE and SSE2 instructions have also been extended to support the eight new XMM registers. SSE and SSE2 are available in 32-bit mode in modern x86 processors; however, if they're used in 32-bit programs, those programs will only work on systems with processors that support them. This is not an issue in 64-bit programs, as all processors that support AMD64 support SSE and SSE2, so using SSE and SSE2 instructions instead of x87 instructions does not reduce the set of machines on which the programs will run. Since SSE and SSE2 are generally faster than, and duplicate most of the features of, the traditional x87 instructions, MMX , and 3DNow! , the latter are redundant under AMD64.


  • '''" or "unchecked buffer" attacks. A similar feature has been available on x86 processors since the 80286 as an attribute of segment descriptors; however, this works only on an entire segment at a time. Segmented addressing has long been considered an obsolete mode of operation, and all current PC operating systems in effect bypass it, setting all segments to a base address of 0 and a size of 4  GiB . AMD was the first x86-family vendor to support no-execute in linear addressing mode. The feature is also available in legacy mode on AMD64 processors, and recent Intel x86 processors, when PAE is used.


  • Removal of older features: A number of "system programming" features of the x86 architecture are not used in modern operating systems and are not available on AMD64 in long (64-bit and compatibility) mode. These include segmented addressing (although the FS and GS segments were retained in vestigial form for compatibility with Windows code)2, the task state switch mechanism, and Virtual-8086 mode. These features do of course remain fully implemented in "legacy mode," thus permitting these processors to run 32-bit and 16-bit operating systems without modification.



Virtual address space details

Although virtual addresses are 64 bits wide in 64-bit mode, current implementations (and any chips known to be in the planning stages) do not allow the entire virtual address space of 264 bytes (16 exbibytes, or about 18×1018 bytes) to be used. Most operating systems and applications will not need such a large address space for the foreseeable future (for example, Windows implementations for AMD64 are only populating 16 tebibytes, or 44 bits' worth), so supporting such wide virtual addresses would simply increase the complexity and cost of address translation with no real benefit. AMD therefore decided that, in the first implementations of the architecture, only the least significant 48 bits of a virtual address would actually be used in address translation (page table lookup). However, bits 48 through 63 of any virtual address must be copies of bit 47 (in a manner akin to Sign Extension ), or an exception will be raised. Addresses complying with this rule are referred to as "canonical form." Canonical form addresses run from 0 through 00007FFF`FFFFFFFF, and from FFFF8000`00000000 through FFFFFFFF`FFFFFFFF, for a total of 248 bytes or 256 tebibytes of usable virtual address space.

This "quirk" allows an important feature for later scalability to true 64-bit addressing:
many operating systems (including, but not limited to, the Windows NT family) take the higher-addressed half of the address space (named kernel space) for themselves and leave the lower-addressed half (user space) for application code, user mode stacks, heaps, and other data regions. The "canonical address" design ensures that every AMD64 compliant implementation has, in effect, two memory halves: the lower half starts at 00000000`00000000 and "grows upwards" as more virtual address bits become available, while the higher half is "docked" to the top of the address space and grows downwards. Also, fixing the contents of the unused address bits prevents their use by operating system as flags, privilege markers, etc., which could become problematic when the architecture is indeed extended to 52, 56, 60 and 64 bits.

The 64-bit addressing mode ("long mode") is a superset of Physical Address Extension s (PAE); because of this, Page sizes may be either 4 KiB (212 bytes) or 2 MiB (221 bytes). However, rather than the three-level Page Table system used by systems in PAE mode, systems running in long mode use four levels of page table: PAE's ''Page-Directory Pointer Table'' is extended from 4 entries to 512, and an additional ''Page-Map Level 4 Table'' is added, containing 512 entries in 48-bit implementations. In implementations supporting larger virtual addresses, this latter table would either grow to accommodate sufficient entries to describe the entire address range, up to a theoretical maximum of 33,554,432 entries for a 64-bit implementation, or be over ranked by a new mapping level, such as a PML5. Either way, a full mapping hierarchy of 4 KiB pages for the whole 48-bit space would take a bit more than 512 GiB of RAM (about 0.196% of the 256 TiB virtual space).


Operating modes



Operating mode explanation

There are two primary modes of operation for this architecture:

;''') Protected Mode applications may be supported.

: Since the basic instruction set is the same, there is no major performance penalty for executing x86 code. This is unlike Intel's IA-64 , where differences in the underlying ISA means that running 32-bit code is like using an entirely different processor. However, on AMD64, 32-bit x86 applications may still benefit from a 64-bit Recompile , due to the additional registers in 64-bit code, which a high-level Compiler can use for optimization.

;Legacy mode: The mode used by 16-bit (protected mode or real mode) and 32-bit operating systems. In this mode, the processor acts just like an x86 processor, and only 16-bit or 32-bit code can be executed. 64-bit programs will not run.


Implementations

The following processors implement the AMD64 architecture:


INTEL 64

Intel 64 is Intel's implementation of x86-64. It is used in newer versions of Pentium 4 , Pentium D , Pentium Extreme Edition , Celeron D , Xeon , and Pentium Dual-Core processors, and in all versions of the Core 2 processors.


History of Intel 64

Historically, AMD has developed and produced processors patterned after Intel's original designs, but with x86-64, roles were reversed: Intel found itself in the position of adopting the architecture which AMD had created as an extension to Intel's own x86 processor line.

Intel's project was originally Codename d Yamhill (after the Yamhill River in Oregon 's Willamette Valley ). After several years of denying its existence, Intel announced at the February 2004 IDF that the project was indeed underway. Intel's chairman at the time, Craig Barrett , admitted that this was one of their worst kept secrets. "Craig Barrett confirms 64 bit address extensions for Xeon. And Prescott", from The Inquirer "A Roundup of 64-Bit Computing", from internetnews.com


Implementations

Intel 64 was originally implemented on the E revision (Prescott) of Pentium 4 line of microprocessors, which were supported by i915P (Grantsdale) and i925X (Alderwood) chipsets in June 2004. This was largely due to the competitive pressure of AMD's AMD64 technology implemented on Opteron and Athlon 64 lines of microprocessing units, otherwise known as the K8 core, one year earlier in 2003; the technology was largely built compatible to AMD64, and the then announced Windows XP Professional X64 Edition supporting AMD64 technology. Intel's first processor to activate the Intel 64 technology was the multi-socket processor Xeon code-named ''Nocona''. Since the Nocona Xeon itself is directly based on Intel's desktop processor, the Pentium 4 , the Pentium 4 also has Intel 64 technology built in, although as with Hyper-Threading , this feature was not initially enabled on the then-new Prescott design, likely because enabling Intel 64 did not coincide with Intel's stance on 64-bit x86 extensions at that particular time. Intel subsequently began selling Intel 64-enabled Pentium 4s using the E0 revision of the Prescott core, being sold on the market as the Pentium 4, model F. However, the revision F core was targeted at workstations. Intel's official launch of Intel 64 (under the name EM64T at that time) in mainstream desktop processors was the N0 Stepping Prescott-2M. The E0 revision also adds eXecute Disable(XD) (Intel's name for the NX Bit ) support to Intel 64, and has been included in the current Xeon code-named ''Irwindale''. All 9xx/8xx/6xx/5x6/5x1/3x6/3x1 series CPUs have Intel 64 enabled, as do the Core 2 CPUs, and as will all future Intel CPUs. Intel 64 is also present in the last members of the Celeron D line.

The first Intel Mobile Processor supporting Intel 64 is the Merom version of the Core 2 processor, which was released on 27 July 2006 . None of Intel's earlier notebook CPUs ( Core Duo , Pentium M , Celeron M , Mobile Pentium 4 ) support Intel 64.

The following processors implement the Intel 64 architecture:


DIFFERENCES BETWEEN AMD64 AND INTEL 64


There are a small number of differences between the two instruction sets. Compilers generally produce binaries that target both AMD64 and Intel 64, making the differences mainly of interest to compiler developers and operating system developers.


Recent implementations

  • Intel 64's BSF and BSR instructions act differently when the source is 0 and the operand size is 32 bits. The processor sets the zero flag and leaves the upper 32 bits of the destination undefined.


  • Intel 64 lacks the ability to save and restore a reduced (and thus faster) version of the Floating-point state (involving the FXSAVE and FXRSTOR instructions).


  • Intel 64 lacks some model-specific registers that are considered architectural to AMD64. These include SYSCFG, TOP_MEM, and TOP_MEM2.


  • AMD64 require a different microcode update format and control MSRs while Intel 64 supports Microcode update as in 32-bit mode.


  • AMD64 lacks the MONITOR and MWAIT instructions, used by operating systems to better deal with Intel's Hyper-threading feature and also to enter specific low power states.


  • AMD64 systems allow the use of the AGP aperture as an IOMMU . Operating systems can take advantage of this to let normal PCI devices DMA to memory above 4 GiB. Intel 64 systems require the use of bounce buffers, which are slower.


  • Intel 64 only supports SYSCALL and SYSRET in IA-32e mode (not in compatibility mode). SYSENTER and SYSEXIT are supported in both modes.

  • AMD64 lacks support for SYSENTER and SYSEXIT in both sub-modes of long mode.


  • Near branches with the 66H (operand size) prefix behave differently. One type of CPU clears only the top 32 bits, while the other type clears the top 48 bits.


  • AMD64 processors extends PSE-36 to 40-bit, but Intel 64 processors don't.



Older implementations

  • Early AMD64 processors lacked the CMPXCHG16B instruction, which is an extension of the CMPXCHG8B instruction present on most post- 486 processors. Similar to CMPXCHG8B, CMPXCHG16B allows for Atomic Operation s on 128-bit double quadword (or oword) data types. This is useful for high resolution counters that could be updated by multiple processors (or cores). Without CMPXCHG16B the only way to perform such an operation is by using a Critical Section .


  • Early Intel CPUs with Intel 64 lacked LAHF and SAHF instructions supported by AMD64 until introduction of Pentium 4 G1 step in December 2005. LAHF and SAHF are load and store instructions, respectively, for certain status flags. These instructions are used for virtualization and floating-point condition handling.


  • Early Intel CPUs with Intel 64 also lack the NX Bit (No Execute bit) of the AMD64 architecture. The NX bit marks memory pages as non-executable, allowing protection against many types of malicious code.


  • Original Intel 64 implementations allowed access only to 236 bytes of physical memory, while AMD64 systems can handle up to 240 bytes (with planned expansion to 256 bytes). However, recent Intel 64 implementations now provide 240 bytes of physical memory access.



MARKET ANALYSIS


AMD's AMD64 design represents a break with the company's past behavior of following Intel's standards, but emulates Intel's earlier behavior of extending the x86 architecture, from the 16-bit 8086 to the 32-bit 80386 and beyond, without ever removing Backward Compatibility .

It was long believed that 64-bit RISC chips such as the DEC Alpha would eventually replace the outdated and quirky x86 architecture (which is a direct descendant from 8-bit processors, such as the 8085 and the Z80 ). Part of the reason this did not happen was the vast investment in application software for x86-based systems. Intel, Cyrix, AMD, and others, also quickly found ways to apply modern design principles (inspired by RISC designs, as well as other ideas) ''transparently'', i.e. without changing the basic programming model. A large company, such as Intel, can also employ the latest low-level implementation techniques, which enhances performance regardless of architecture. Furthermore, the 8-bit heritage of the x86 processor line actually helps making good use of limited cache memories, thanks to an inherent small code footprint.

Part of the reason is also that the worst performance problems of the original 8086 and 8087 chips, such as the slow bus-interface, were quickly fixed by the advent of the 80186 and 80286. The 80286 also introduced Protected Mode , allowing a fully protected OS to be developed for it (though the protection was segment-based), and increased the physical address space to 24 bits. Registers were still 16 bits however, meaning that the same segment size limitations as in 8088 still applied, though the segmentation was changed to support a larger segmented address space (up to 8192 segments globally and per task, each up to 65536 bytes in size) and also protection. The 80386 (in 1985) then extended the registers to 32 bits, and extended the size of the linear address space, accessible without use of the segmentation architecture, to 2^32 bytes. The 80386 also added paging scheme on the bottom of the (now "optional") segmentation. The remaining performance hampering quirks of the original design, such as the stacked x87 registers, has been both largely factored out (by register renaming and other techniques) and, lately, successively replaced, without losing backward compatibility. The x86-64 architecture finally migrates the x86 architecture into a fully 64-bit environment, while maintaining compatibility with legacy applications.

As Of 2006 , most consumer and business applications have not evolved into 64-bit aware software. Most current software applications do not need to address more than 2  GiB of address space. Nevertheless, their chips' cost-effectiveness has allowed AMD to capture a larger share of the personal computer market, at Intel's expense, simply because of the performance-to-cost ratio and the expected growth capability should 64-bit applications become common. Intel in the summer of 2006 had announced a substantial reduction in net revenue and major restructuring.


OPERATING SYSTEM SUPPORT

The following operating systems and releases support the x86-64 architecture in Long Mode :


DOS

It is possible to enter long mode under DOS with a DOS Extender similar to DOS4GW . DOS itself is not aware of that and no benefits should be expected unless running DOS in an emulation with an adequate virtualization driver backend, for example: the mass storage interface.

BSD


FreeBSD

FreeBSD first added x86-64 support as an experimental architecture in 5.1-RELEASE, in June 2003. It was included as a standard distribution architecture as of 5.2-RELEASE, in January 2004. Since then, FreeBSD has designated the x86-64 architecture as a Tier 1 platform. The 6.0-RELEASE version cleaned up some quirks with running 32-bit executables under AMD64, and most drivers work just as they do on 32-bit x86 architectures. Work is currently being done to integrate more fully the 32-bit x86 Application Binary Interface (ABI), in the same manner as the Linux 32-bit ABI compatibility currently works. Within the FreeBSD environment and developer code base, the x86-64 architecture is usually referred to as "amd64".


NetBSD

Support for the x86-64 architecture was first committed to the NetBSD source tree on 19 June 2001 . As of NetBSD 2.0, released on 9 December 2004 , ''NetBSD/amd64'' is a fully integrated and supported port.


OpenBSD

OpenBSD has supported AMD64 since OpenBSD 3.5, released on 1 May 2004 . Complete in-tree support for the platform was achieved prior to the hardware's initial release due to AMD's loaning of several machines for the project's Hackathon that year. OpenBSD Developers have taken to the platform because of its use of the NX Bit , which allowed for an easy implementation of the W^X feature.

The code for the AMD64 port of OpenBSD also runs on Intel 64 processors which contains cloned support for the AMD64 extensions, but since Intel left out support for the page table NX bit in early Intel 64 processors, there is no W^X support on those Intel CPUs; later Intel 64 processors added support for the NX bit under the name "XD bit". Symmetric Multiprocessing (SMP) is supported on OpenBSD's AMD64 port, starting with release 3.6 on 1 November 2004 .


Linux

See Also: List of 64-bit Linux distributions



Linux was the first operating system kernel to run the x86-64 architecture in long mode, starting with the 2.4 version prior to the physical hardware's availability. Linux also provides backward compatibility for running 32-bit executables. This permits programs to be recompiled into long mode while retaining the use of 32-bit programs. Several Linux distributions currently ship with x86-64-native kernels and Userlands . Some, such as SUSE , Mandriva and Debian GNU/Linux package both 32-bit and 64-bit systems on a single DVD-ROM image to allow automatic selection of the best software during installation.


Mac OS X

and higher support 64-bit command-line tools when run on 64-bit Intel-based machines, just as version 10.4 and higher support them on 64-bit PowerPC machines. Apple - Mac OS X Xcode 2.4 Release Notes: Compiler Tools


MenuetOS

The AMD64 version of MenuetOS was released in June 2005. Although MenuetOS was originally written for 32-bit x86 architectures and released under the GPL, the AMD64 version is proprietary. It is distributed as Freeware with the source code for some components.


Solaris

Solaris 10 and later releases support the x86-64 architecture. Just as with the SPARC architecture, there is only one operating system image for all 32-bit and 64-bit x86 systems; this is labeled as the "x86/x64" DVD-ROM image.

Default behavior is to boot a 64-bit kernel, allowing both 64-bit and existing or new 32-bit executables to be run. A 32-bit kernel can also be manually selected, in which case only 32-bit executables are supported. The isainfo command can be used to determine if a system is running a 64-bit kernel.


Windows

x64 editions of Microsoft Windows client and server, Windows XP Professional X64 Edition and Windows Server 2003 SP1 x64 Edition, were released in March 2005. Internally they are actually the same build (5.2.3790.1830 SP1), as they share the same source base and operating system binaries, so even system updates are released in unified packages, much in the manner as Windows 2000 Professional and Server editions for x86. Windows Vista x64, which also has many different versions, was released in January 2007. Windows for x64 has the following characteristics:
  • 8  Tebibyte s (243 bytes) of user mode virtual address space per process. A 64-bit program can use all of this, subject of course to backing store limits on the system. This is a 4096-fold increase over the default 2  Gibibyte user-mode virtual address space offered by 32-bit Windows.

  • 8  Tebibyte s (243 bytes) of kernel mode virtual address space for the operating system. Again, this is a 4096-fold increase over 32-bit Windows versions. The increased space is primarily of benefit to the file system cache and kernel mode "heaps" (non-paged pool and paged pool).

  • Support for up to 128  GiB (Windows XP) or 1  TiB (Windows Server 2003) of RAM.

  • LLP64 data model: "int" and "long" types are still 32 bits wide, while pointers and types derived from pointers are 64 bits wide.

  • Device drivers must be 64-bit versions; there is no support for running 32-bit kernel-mode executables within the 64-bit OS.

  • Support for running existing 32-bit applications (.exe's) and dynamic link libraries (.dll's). A 32-bit program, if linked with the "large address aware" option, can use up to 4 gibibytes of virtual address space, as compared to the default 2 gibibytes (optional 3 gibibytes with /3GB boot.ini option and "large address aware" link option) offered by 32-bit Windows.

  • 16-bit DOS and Windows (Win16) applications will not run on x64 versions of Windows due to removal of NTVDM .

  • Full implementation of the NX (No Execute) page protection feature. This is also implemented on recent 32-bit versions of Windows when they are started in PAE mode.

  • As in x86 versions of the Windows NT family, the FS and GS segment descriptors are used to point to two operating system defined structures: the Thread Information Block and Processor Control Region, respectively. Thus, for example, {Link without Title} :0 is the address of the first member of the Thread Information Block. Maintaining this convention made the x64 port easier, but required AMD to retain the function of the FS and GS segments in long mode — even though segmented addressing ''per se'' is not really used by any modern operating system.

  • Early reports claimed that the operating system scheduler would not save and restore the x87 FPU machine state across thread context switches. Observed behavior shows that this is not the case: the x87 state is saved and restored, except for kernel-mode-only threads. Nevertheless, the most recent documentation available from Microsoft states that the x87/MMX/3DNow! instructions may not be used in long mode.

  • Some components like Microsoft Jet Database Engine and Data Access Objects will not be ported to 64-bit architectures such as x86-64 and IA-64. Microsoft Developer Network - General Porting Guidelines (64-bit Windows Programming) Microsoft Developer Network - Data Access Road Map



INDUSTRY NAMING CONVENTIONS

  Url http://listsapplecom/archives/Darwin-dev/2006/Aug/msg00095html
  Title re: Intel XNU bug report
  Accessdate 2006-10-05
  Author Kevin Van Vechten
  Date August 9 , 2006
  Work Darwin-dev mailing list
  Publisher Apple Computer
  Quote The kernel and developer tools have standardized on "x86_64" for the name of the Mach-O architecture



Similarly, Microsoft began using "x64" as a vendor-neutral way to refer to products that support both AMD64 and Intel 64. Other companies, such as Sun Microsystems , have also adopted this convention.

Many operating systems introduced support for x86-64 prior to Intel announcing its own implementation of the architecture, and thus adopted the name of the only implementation at the time, "AMD64" (or "amd64"):

  • Microsoft Windows : x64 versions of Windows use the AMD64 moniker to designate various components which use 64-bit technology for IA-32 processors. For example, the system folder on a Windows x64 Edition installation CD-ROM is named "AMD64", in contrast to "i386" in 32-bit versions.


  • Solaris : the isalist command in Sun's Solaris operating system identifies both AMD64- and Intel 64–based systems as "amd64"


  • Debian GNU/Linux supports both AMD64 and Intel 64 under the architecture name "amd64".


  • BSD systems such as FreeBSD , NetBSD and OpenBSD support both AMD64 and Intel 64 under the architecture name "amd64".


See the History Of Intel 64 section of this article for the various names used by Intel.


SEE ALSO



NOTES AND REFERENCES



EXTERNAL LINKS