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Perhaps surprisingly, there are at least three different conventions for counting the quantity of data transferred in the numerator of Bytes/second . # ''bcopy convention'': counts the amount of data copied from one location in memory to another location per unit time. For example, copying 1 million bytes from one location in memory to another location in memory in one second would be counted as 1 million bytes per second. # ''STREAM convention'': sums the amount of data that the application code explicitly reads plus the amount of data that the application code explicitly writes. Using the previous 1 million byte copy example, the ''STREAM'' bandwidth would be counted as 1 million bytes read plus 1 million bytes written in one second, for a total of 2 million bytes per second. # ''hardware convention'': counts the actual amount of data read or written by the hardware, whether the data motion was explicitly requested by the user code or not. Using the same 1 million byte copy example, the ''hardware'' bandwidth on computer systems with a ''write allocate'' Cache policy would include an additional 1 million bytes of traffic because the hardware reads the target array from memory into cache before performing the stores. This gives a total of 3 million bytes per second actually transferred by the hardware. The ''bcopy convention'' is self-consistent, but is not easily extended to cover cases with more complex access patterns, for example three reads and one write. The ''STREAM convention'' is most directly tied to the user code, but may not count all the data traffic that the hardware is actually required to perform. The ''hardware convention'' is most directly tied to the hardware, but may not represent the minimum amount of data traffic required to implement the user's code. For example, some computer systems have the ability to avoid ''write allocate'' traffic using special instructions, leading to the possibility of misleading comparisons of bandwidth based on different amounts of data traffic performed. Memory bandwidth that is advertised for a given memory or system is usually the maximum theoretical bandwidth. In practice the observed memory bandwidth will be less than (and is guaranteed not to exceed) the advertised bandwidth. A variety of Computer Benchmarks exist to measure sustained memory bandwidth using a variety of access patterns. These are intended to provide insight into the memory bandwidth that a system should sustain on various classes of real applications. COMPUTATION Theoretical maximum memory bandwidth is typically computed by multiplying the width of the interface by the '''frequency''' at which it transfers data. This is also referred to as the '''burst rate''' of the interface, in recognition of the possibility that this rate may not be sustainable over long periods (i.e., the Throughput may be less than the theoretical maximum memory bandwidth). The nomenclature standards often differ across memory technologies, but for commodity DDR SDRAM and DDR2 SDRAM memory the computation is:
So a recent computer system with a dual-channel configuration and two DDR2-800 modules, each running at 400 MHz (actual bus speed, which is half of the nominal speed of 800 Mhz, but in DDR2 is twice the memory's actual clock of 200 MHz), would have a theoretical maximum memory bandwidth of:
As of 2007, advanced personal computers and graphics cards use even more combined busses than Dual-channel , and combine four (e.g. Mac Pro), five (e.g. nVidia 8800GTS), six (e.g. nVidia 8800GTX) or more sets of 64-bit memory modules and busses to reach 256-bit, 320-bit, 384-bit or greater total memory bandwidth. In this sort of multi-channel configuration, memory must be broken out so that there is a 64-bit wide chip or module for each channel. So for a 256-bit wide 4GB configuration with DDR2 modules one must have 4 1GB modules since each is only capable of 64-bits. EXTERNAL LINKS |
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