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Data on the interface is framed using the IEEE Ethernet standard. As such it consists of a preamble, start of frame delimiter, Ethernet headers, protocol specific data and a Cyclic Redundancy Check (CRC) checksum.

The GMII interface is defined in IEEE Standard 802.3, 2000 Edition
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TRANSMITTER

  • GTXCLK - clock signal for gigabit TX.. signals (125 MHz)

  • TXCLK - clock signal for 10/100 Mbit signals

  • TXD {Link without Title} - data to be transmitted

  • TXEN - transmitter enable

  • TXER - transmitter error (used to corrupt a packet)



Notes on transmit clocks

There are two clocks, depending on whether the PHY is operating at gigabit or 10/100 Mb speeds. For gigabit speeds, the GTXCLK is supplied to the PHY and the TXD, TXEN, TXER signals are synchronized to this. Otherwise for 10/100 Mb the TXCLK (supplied by PHY) is used for synchronizing those signals. This operates at either 25 MHz for 100 Mb or 2.5 MHz for 10 Mb connections. The receiver clock is much simpler, with only one clock, which is recovered from the incoming data. Hence the GTXCLK and RXCLK are not coherent.


RECEIVER

  • RXCLK - received Clock Signal (recovered from incoming received data)

  • RXD {Link without Title} - received data

  • RXDV - signifies data received is valid

  • RXER - signifies data received has errors

  • COL - Collision Detect (half-duplex connections only)

  • CRS - Carrier Sense (half-duplex connections only)



MANAGEMENT

  • MDC - Management interface clock

  • MDIO - Management interface I/O bidirectional pin.


The management interface controls the behaviour of the PHY. There are 32 addresses, each containing 16 bits. The first 16 addresses have a defined usage (see "IEEE 802.3,2000-22.2.4 Management Functions"), while the others are device specific. These registers can be used to configure the device (say "only gigabit, full duplex", or "only full duplex") or can be used to determine the current operating mode.


SEE ALSO