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FEC devices are often located close to the receiver of an analog signal, in the first stage of digital processing after a signal has been received. That is, FEC circuits are often an integral part of the analog-to-digital conversion process. Many FEC coders can also generate a Bit-error Rate (BER) signal which can be used as feedback to fine-tune the analog receiving electronics. Many FEC algorithms, such as the Viterbi Algorithm , can take (quasi-) analog data in, and generate digital data on output. The maximum fraction of errors that can be corrected is determined in advance by the design of the code, so different forward error correcting codes are suitable for different conditions. HOW IT WORKS FEC is accomplished by adding Redundancy to the transmitted information using a predetermined algorithm. Each redundant bit is invariably a complex function of many original information bits. The original information may or may not appear in the encoded output; codes that include the unmodified input in the output are systematic, while those that do not are '''nonsystematic'''. An extremely simple example would be an analog to digital converter that samples three bits of signal strength data for every bit of transmitted data. If the three samples are mostly all zero, the transmitted bit was probably a zero, and if three samples are all one, the transmitted bit was probably a one. The simplest example of error correction is for the receiver to assume the correct output is given by the most frequently occurring value in each group of three. This allows an error in any one of the three samples to be corrected by "democratic voting". In practice, this is a very poor FEC, but it does illustrate the principle. In practice, FEC codes typically examine the last several dozen, or even the last several hundred, previously received bits to determine how to decode the current small handful of bits (typically in groups of 2 to 8 bits). AVERAGING NOISE TO REDUCE ERRORS FEC could be said to work by "averaging noise"; since each data bit affects many transmitted symbols, the corruption of some symbols by noise usually allows the original user data to be extracted from the other, uncorrupted received symbols that also depend on the same user data. This is somewhat analogous to the way that insurance companies and mutual funds manage and spread risk.
TYPES OF FEC The two main categories of FEC are Block Coding and Convolutional Coding .
There are many types of block codes, but the most notable is Reed-Solomon Coding because of its widespread use on the Compact Disc , the DVD , and in computer hard drives. Golay , BCH and Hamming codes are other examples of block codes. Hamming ECC is commonly used to correct NAND Flash memory errors. This provides single-bit error correction and 2 bit error detection. Hamming codes are only suitable for more reliable single level cell (SLC) NAND. More dense multi level cell (MLC) NAND requires stronger multi-bit correcting ECC such as BCH or Reed-Solomon. Nearly all block codes apply the algebraic properties of Finite Field s. CONCATENATE FEC CODES TO REDUCE ERRORS Block and convolutional codes are frequently combined in concatenated coding schemes in which the convolutional code does most of the work and the block code (usually Reed-Solomon) "mops up" any errors made by the convolutional decoder.
TURBO CODES The most recent (early 1990s) development in error correction is Turbo Coding , a scheme that combines two or more relatively simple convolutional codes and an Interleaver to produce a block code that can perform to within a fraction of a decibel of the Shannon Limit .
SEE ALSO REFERENCES
United States Patent 7187583 "Method for reducing data error when flash memory storage device using copy back command"] EXTERNAL LINKS |
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