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For the analogue to digital converter, ADC, the method can be thought of as a voltage controlled oscillator, where the controlling voltage is the voltage to be measured and where linearity and proportionality are determined by a negative feedback loop. The output of the oscillator is a pulse stream, each pulse of which is a known, constant, amplitude and duration but variable separating interval. The interval between pulses is determined by the feedback loop so that a low input voltage produces a long interval between pulses and a high input voltage produces a short interval between pulses. Counting the pulses produced in the way described above in a fixed summing interval produces a count proportional to the input voltage to be measured. Variations in scaling can be produced by either varying the fixed summing interval or by counting down the pulses by a fixed ratio or both methods can be used. The output count finally produced is the digitization of the input voltage. The pulses described above may be treated as the Dirac δ (delta) function in a formal analysis and the count as Σ (sigma). Fig.1 is a simplfied block diagram of the Delta Sigma analogue to digital converter. Shown below the block diagram are waveforms at points designated by numbers 1 to 5 for an input of 0.2 volts on the left and 0.4 volts on the right. In most practical applications the summing interval is large compared with the impulse duration and for signals which are a significant fraction of full scale the variable separating interval is also small compared with the summing interval. The Nyquist criteria requires two samples to render a varying input signal. The a samples appropriate to this criteria are two successive Σ counts. The summing interval, which must accommodate a large count in order to achieve adequate precision, is inevitably long so that the converter can only render relatively low frequencies. Hence it is convenient and fair to represent the input voltage (1) as constant over a few impulses. Consider first the waveforms on the left. 1 is the input and for this short interval is constant at 0.2V. The stream of delta impulses is shown at 2 and the difference between 1 and 2 is shown at 3. This difference is integrated to produce the waveform 4. The threshold detector generates a pulse 5 which is sustained until the waveform 4 falls below the threshold. Within the loop 5 triggers the impulse generator and external to the loop increments the counter. The summing interval is a prefixed time and at its expiry the count is strobed into the buffer and the counter reset. It is necessary that the ratio between the impulse interval and the summing interval is equal to the maximum (full scale) count. It is then possible for the impulse duration and the summing interval to be defined by the same clock with a suitable arrangement of logic and counters. This has the advantage that neither interval has to be defined with absolute precision as only the ratio is important. Then to achieve overall accuracy it is only necessary that the amplitude of the impulse be accurately defined. On the right the input is now 0.4V and the sum during the impulse is -0.6V as opposed to -0.8V on the left. Thus the negative slope during the impulse is lower on the right than on the left. Also the sum is 0.4V on the right during the interval as opposed to 0.2V on the left. Thus the positive slope outside the impulse is higher on the right than on the left. The resultant effect is that the integral (4) crosses the threshold more quickly on the right than on the left. A full analysis would show that in fact the interval between threshold crossings on the right is half that on the left. Thus the frequency of impulses is doubled. Hence the count increments at twice the speed on the right to that on the left which is consistent with the input voltage being doubled. In fact the frequency is proportional to the input voltage and so the accumulated count is proportional to the input voltage and with an exact amplitude for the impulse the count is the exact digitization of the input voltage over the summation period. NB. The above description shows why the impulse is called delta.The integral of an impulse is a step. A one bit DAC may be expected to produce a step and so must be a conflation of an impulse and an integration. Analyses which treat the impulse as the output of a 1 bit DAC hide the structure behind the name (sigma delta) and cause confusion and difficulty interpreting the name as an indication of function. Such analyses are very widespread but are deprecated. The digital to analogue converter, DAC arrangement can be thought of as open loop with a counter, Sigma, which is preloaded with the number to be converted. the counter is counted down to zero by a series of impulses, delta. As above these impulses are of fixed ampltude and duration. At the start an integrator is set to zero and then integrates the impulses to form the analogue voltage equivalent of the starting number. DERIVATION FROM Δ-MODULATION ΔΣ modulation is derived from another kind of conversion known as Delta Modulation . In Fig.2, is shown, in a simplified way, how this derivation is done: # Start with a block diagram of a Δ-modulator/demodulator. # The linearity property of the integral operation () makes it possible to move the integrator, which reconstructs the analog signal in the demodulator section, in front of the Δ-modulator. # Again, the linearity property of the integral operation allows the two integrators to be combined and a ΔΣ-modulator/demodulator block diagram is obtained. The spectrum shaping of the two types of modulation is different: ΔΣ-modulation shapes the noise, leaving the signal as it is, while Δ-modulation shapes both noise and signal equally. In general, ΔΣ has some advantages versus Δ modulation:
PRINCIPLE The principle of the ΔΣ architecture is to make rough evaluations of the signal, to measure the error, integrate it and then compensate for that error. The mean output value is then equal to the mean input value if the integral of the error is finite. A demonstration applet is available online to simulate the whole architecture. Analog Devices : Virtual Design Center : Interactive Design Tools : Sigma-Delta ADC Tutorial The number of integrators, and consequently, the numbers of feedback loops, indicates the ''order'' of a ΔΣ-modulator; a 2nd order ΔΣ modulator is shown in Fig. 3. First order modulators are stable, but for higher order ones stability must be taken into great account. The modulator can also be classified by the number of bits it has in output, which strictly depends on the output of the quantizer. The quantizer can be realized with a ''N-level'' comparator, thus the modulator has ''log2N''-bit output; for instance, a 1-bit modulator has a quantizer realized as a simple ''2-level'' comparator (a comparator referred to ''0''), whose output is ''1'' or ''0'' if the input signal is positive or negative. QUANTIZATION THEORY FORMULAS See Also: Quantization When a signal is quantized, the resulting signal approximately has the second-order statistics of a signal with independent additive white noise. Assuming that the signal value is in the range of one step of the quantized value with an equal distribution, the root mean square value of this quantization noise is : In reality, the quantization noise is of course not independent of the signal; this dependence is the source of idle tones and pattern noise in Sigma-Delta converters. Oversampling ratio, where is the sampling frequency and is Nyquist Rate : The rms noise voltage within the band of interest can be expressed in terms of OSR : STRUCTURES The MASH (Multi-stAge noise SHaping) structure has a Noise Shaping property, and is commonly used in digital audio and fractional-N frequency synthesizers. It comprises two or more cascaded overflowing accumulators, each of which is equivalent to a first-order sigma delta modulator. The carry outputs are combined through summations and delays to produce a binary output, the width of which depends on the number of stages (order) of the MASH. Besides its noise shaping function, it has two more attractive properties:
OVERSAMPLING See Also: Oversampling Let's consider a signal at frequency and a sampling frequency of much higher than Nyquist rate (see Fig. 4). ΔΣ modulation is based on the technique of oversampling to reduce the noise in the band of interest (green), which also avoids the use of high-precision analog circuits for the '' Anti-aliasing '' filter. The quantization noise is the same both in a Nyquist converter (in yellow) and in an oversampling convertor (in blue), but it is distributed over a larger spectrum. In ΔΣ-converters, noise is further reduced at low frequencies, which is the band where the signal of interest is, and it is increased at the higher frequencies, where it can be filtered. This property is known as ''noise shaping''. For a first order delta sigma modulator, the noise is shaped by a filter with transfer function . Assuming that the sampling frequency , the quantization noise in the desired signal bandwidth can be approximated as: . Similarly for a second order delta sigma modulator, the noise is shaped by a filter with transfer function . The in-band quantization noise can be approximated as: . In general, for a -order ΔΣ-modulator, the variance of the in-band quantization noise: . When the sampling frequency is doubled, the signal to quantization noise is improved by for a -order ΔΣ-modulator. Higher the oversampling ratio, the higher the Signal-to-noise Ratio and the higher the resolution in bits. Another key aspect given by oversampling is the speed/resolution tradeoff. In fact, the decimation filter put after the modulator not only filters the whole sampled signal in the band of interest (cutting the noise at higher frequencies), but also reduces the frequency of the signal increasing its resolution. This is obtained by a sort of ''averaging'' of the higher data rate bitstream. Example of decimation Let's have, for instance, an 8:1 decimation filter and a 1-bit bitstream; if we have an input stream like 10010110, counting the number of ones, the decimation result is 4/8 = 0.5 = 100 in binary; in other words,
NAMING As can be easily recognized from a previous section, the name ''Delta-Sigma'' comes directly from the presence of a Delta modulator and an integrator, as firstly introduced by Inose et al. in their patent application.H. Inose, Y. Yasuda, J. Murakami, "A Telemetering System by Code Manipulation -- ΔΣ Modulation," IRE Trans on Space Electronics and Telemetry, Sep. 1962, pp. 204-209. Very often, the name ''Sigma-Delta'' is used as a synonym, but nowadays IEEE publications mostly use ''Delta-Sigma''. NOTES SEE ALSO EXTERNAL LINKS
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