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A boolean circuit with ''n'' input Bit s is a Directed Acyclic Graph in which every node (usually called ''gates'' in this context) is either an input node of In-degree 0 labeled by one of the ''n'' input bits, an AND Gate , an OR or a NOT Gate . One of these gates is designated as the output gate. Such a circuit naturally computes a function of its ''n'' inputs. The size of a circuit is the number of gates it contains and its depth is the maximal length of a path from an input gate to the output gate.

The circuit-size (respectively circuit-depth) complexity of a boolean function ''f'' is the minimal size (respectively minimal depth) of any circuit computing ''f''. The goal of circuit complexity is to determine this optimal size/depth for natural families of boolean functions. Most often the challenge involves the study of the Asymptotic Behavior of size or depth complexity for sequences of boolean functions f_1, f_2, ... where each f_n is a function of ''n'' bits.

Complexity Class es defined in terms of boolean circuits include AC0 , AC , TC0 and NC .


UNIFORMITY


Boolean circuits are one of the prime examples of so-called Non-uniform Models Of Computation in the sense that inputs of different lengths are processed by different circuits, in contrast with uniform models such as Turing Machine s where the same computational device is used for all possible input lengths. An individual Computational Problem is thus associated with a particular ''family'' of boolean circuits C_1, C_2, ... where each C_n is the circuit handling inputs of ''n'' bits. A Uniformity condition is often imposed on these families so that each individual circuit can be computed by some Resource-bounded Turing machine.


HISTORY


In his 1999 book on circuit complexity, Vollmer states (pg. 1) that "the direction which ''complexity theoretic research on circuits'' took was heavily influenced by Savage's textbook", citing Savage 1976.


Key results

  • The boolean function PARITY, which is 1 if and only if the sum of its input bits is odd, does not lie in AC^0. The result was first established independently by Ajtai (1983) and by Furst, Saxe and Sipser (1984). Later improvements by Hastad (1987) in fact establish that any family of AC^0 computing PARITY requires exponential size. Smolensky (1986) proved that this is true even if the circuit is augmented with gates computing the sum of its input bits modulo some prime p.

  • The monotone function CLIQUE cannot be computed by a polynomial-size family of monotone circuits (that is, circuits with AND and OR gates but no negation). This original result of Razborov (1985) was later improved to an exponential-size lower bound by Alon and Boppana (1987). Raz and McKenzie later showed that the monotone NC hierarchy is infinite (1999).

  • Division lies in uniform TC0 (Hesse 2001).



COMPLEXITY CLASSES


Many circuit complexity classes are defined in terms of class hierarchies. For each integer ''i'', there is a class NCi , consisting of polynomial-size circuits of depth O(\log^i(n)), using bounded fan-in AND, OR, and NOT gates. We can talk about the union NC of all of these classes. By considering unbounded fan-in gates, we construct the classes ACi and AC. We construct many other circuit complexity classes with the same size and depth restrictions by allowing different sets of gates.


REFERENCES