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| parallel computing | |
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Cache line most commonly is in states "dirty", "invalid" and "valid" or "shared". On read miss, request for read is broadcast on the bus. All cache controllers are monitoring the bus. The one having the copy in the state "dirty" changes it state to "valid" and sends the copy to requesting node. On write miss, invalidation of all cache copies is performed. When writing a block in state "valid", its state is changed to "dirty" and a broadcast is sent out to all cache controllers to invalidate their copies. Since ''snooping'' does not scale well, larger CcNuma systems tend to use Directory-based Coherence Protocols . IMPLEMENTATION The cache would have 3 extra bits V: valid D: Dirty bit, signifies that data in the cache is not the same as in memory S: Shared |
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