Information AboutVerilog |
| CATEGORIES ABOUT VERILOG | |
| hardware description languages | |
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Verilog is a Hardware Description Language (HDL) used to model Electronic Systems . The language (sometimes called ''Verilog HDL'') supports the design, verification, and implementation of Analog , Digital , and Mixed-signal Circuit s at various levels of Abstraction . The designers of Verilog wanted a language with syntax similar to the C Programming Language so that it would be familiar to engineers and readily accepted. The language is Case-sensitive , has a Preprocessor like C, and the major Control Flow Keyword s, such as "if" and "while", are similar. The formatting mechanism in the printing routines and language Operators and their Precedence are also similar. The language differs in some fundamental ways. Verilog uses Begin/End instead of curly braces to define a block of code. The definition of constants in Verilog require a bit width along with their base, consequently these differ. Verilog 95 and 2001 don't have structures, pointers, or recursive subroutines, however SystemVerilog now includes these capabilities. Finally, the concept of time —so important to a HDL— won't be found in C. The language differs from a conventional Programming Language in that the execution of Statements is not strictly linear. A Verilog design consists of a hierarchy of modules. Modules are defined with a set of input, output, and bidirectional ports. Internally, a module contains a list of wires and registers. Concurrent and sequential statements define the behaviour of the module by defining the relationships between the ports, wires, and registers. Sequential statements are placed inside a begin/end block and executed in sequential order within the block. But all concurrent statements and all begin/end blocks in the design are executed in parallel. A module can also contain one or more instances of another module to define sub-behavior. A subset of statements in the language is Synthesizable . If the modules in a design contain only synthesizable statements, software can be used to transform or synthesize the design into a Netlist that describes the basic components and connections to be implemented in hardware. The netlist may then be transformed into, for example, a form describing the Standard Cell s of an Integrated Circuit (e.g. an ASIC ) or a Bitstream for a Programmable Logic Device (e.g. a FPGA ). HISTORY Beginning Verilog was invented by Phil Moorby and Prabhu Goel at Automated Integrated Design Systems (later renamed to Gateway Design Automation ) in 1985 as a hardware modeling language. Gateway Design Automation was later purchased by Cadence Design Systems in 1990 . Cadence now has full proprietary rights to Gateway's Verilog and the Verilog-XL simulator Logic Simulator s. Verilog-95 With the increasing success of VHDL at the time, Cadence decided to make the language available for open Standardization . Cadence transferred Verilog into the public domain under the Open Verilog International (OVI) (now known as Accellera ) organization. Verilog was later submitted to IEEE and became IEEE Standard 1364-1995, commonly referred to as Verilog-95. Verilog 2001 Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies that users had found in the original Verilog standard. These extensions became IEEE Standard 1364-2001 known as Verilog-2001.
Verilog-2001 is the dominant flavor of Verilog supported by the majority of commercial EDA software packages. Verilog 2005 Not to be confused with SystemVerilog , ''Verilog 2005'' ( IEEE Standard 1364-2005) consists of minor corrections, spec clarifications, and a few new language features (such as the uwire keyword.) A separate part of the Verilog standard , Verilog-AMS , attempts to integrate analog and mixed signal modelling with traditional Verilog. SystemVerilog See Also: SystemVerilog Systemverilog is a superset of Verilog-2005, with many new features and capabilities to aid design-verification and design-modeling. The advent of High Level Verification languages such as OpenVera , and Verisity 's E language encouraged the development of Superlog by Co-Design Automation Inc . Co-Design Automation Inc was later purchased by Synopsys . The foundations of Superlog and Vera were donated to Accellera , which later became the IEEE standard P1800-2005: SystemVerilog. EXAMPLE A Hello World Program looks like this:
A simple example of two Flip-flops follows:
The "<=" operator in verilog is another aspect of its being a hardware description language as opposed to a normal procedural language. This is known as a "non-blocking" assignment. When the simulation runs, all of the signals assigned with a "<=" operator have their assignment scheduled to occur after all statements occurring during the same point in time have executed. After all the statements have been executed for one event, the scheduled assignments are performed. This makes it easier to code behaviours that happen simultaneously. In the above example, flop1 is assigned flop2, and flop2 is assigned flop1. These statements are executed during the same time event. Since the assignments are coded with the "<=" non-blocking operator, the assignments are scheduled to occur at the end of the event. Until then, all reads to flop1 and flop2 will use the values they had at the beginning of the time event. This means that the order of the assignments are irrelevant and will produce the same result. flop1 and flop2 will swap values every clock. The other choice for assignment is an "=" operator and this is known as a blocking assignment. When the "=" operator is used, things occur in the sequence they occur much like a procedural language. In the above example, if the statements had used the "=" blocking operator instead, then the order of the statements would affect the behaviour. If the same code were used but changed to "=" operators, the reset would set flop2 to a 1, and flop1 to a 0. A clock event would set flop1 to flop2 (a 1) and this assignment would happen immediately. The next statement would assign flop2 to flop1, which is now a 1. Rather than swap values every clock, flop1 and flop2 would both become 1 and remain that way. An example Counter circuit follows:
An example of delays:
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