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The operation of a Synchronous PRAM can result in simultaneous access by multiple Processor s to the same location in Shared Memory . There are several variants of our PRAM model, depending on whether such simultaneous access is permitted or prohibited. As accesses can be ''reads'' or ''writes'', there are four possibilities: # Exclusive Read Exclusive Write (EREW) - every memory cell can be read or written to by only one processor at a time # Concurrent Read Exclusive Write (CREW) - multiple processors can read a memory cell but only one can write at a time # Exclusive Read Concurrent Write (ERCW) - never considered # Concurrent Read Concurrent Write (CRCW) - multiple processors can read and write ::Common CRCW - if processors writing the same value, OK; otherwise, it is an illegal operation ::Arbitrary CRCW - one attempt is successful (we don't know which in advance), others retire ::Priority CRCW - rank indicates who gets to write Algorithms are written in pseudo-code as there is no actual implementation of a PRAM, (except University of Maryland James Clark School of Engineering as yet unnamed machine) . However, these kinds of algorithms are useful for understanding the exploitation of concurrency, dividing the original problem into similar sub-problems and solving them in parallel. SEE ALSO EXTERNAL LINKS University Of Maryland's prototype PRAM REFERENCES 1 |
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