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The PDP-11 was a series of 16-bit Minicomputer s sold by Digital Equipment Corp. in the 1970s and 1980s. The PDP-11 was a successor to DEC's PDP-8 computer in the PDP series of computers. It had several uniquely innovative features, and was easier to program than its predecessors. It was well-liked by programmers, and it was replaced in the mid-range minicomputer niche by the VAX-11 32-bit extension of the PDP-11. Much of the market for both machines would be taken by Personal Computer s, including the IBM PC and Apple II , and Workstations , such as those from Sun Microsystems . UNIQUE FEATURES OF THE PDP-11 SERIES Instruction set Programmers liked the PDP-11 design because it had a highly- Orthogonal Instruction Set which allowed them to separately memorize all of the operations and the methods of accessing Operand s. They could then predict that any access method (or " Addressing Mode ") would work with any operation; they did not have to learn a list of exceptions or special cases in which an operation had a special or restricted set of addressing modes.
In some logical sense, the set of addressing modes provided one "basis", and the set of operations provided another. Each two-operand instruction was separated into two six-bit operand identifiers (each consisting of a three-bit register number, and a three-bit addressing mode) and a four-bit Op-code ; single-operand instructions had one six-bit operand identifier, and a ten-bit op-code. All op-codes operated with any operand identifier address mode (or combination of them, for the two-operand instructions). Of the 8 registers (numbered 0 through 7), 7 were general-purpose and could be used for most purposes, although register 6 was specially recognized by the hardware as the Stack Pointer for some instructions; register 7 was the Program Counter . This latter innovation, together with some of the addressing modes, provided constants, Absolute Addresses , and relative (position independent) addressing. 16-bit words were stored Little-endian with least significant bytes first. 32-bit words were often stored in an unusual Middle-endian format. Due to the popularity of the PDP-11, this format is still sometimes referred to as ''pdp-endian''. No dedicated I/O bus In the most radical departure from other, earlier computers, the initial models of the PDP-11 had no dedicated Bus for Input/output ; it had only a memory bus called the Unibus . All input and output devices were Mapped To Addresses In Memory , so no special I/O instructions were needed. The Interrupt system was intentionally designed to be as simple as possible, while ensuring that no event in an interrupt sequence could be missed. A device would request an interrupt by asserting a common input into one of four priority lines; the processor would respond over an interrupt Daisy Chain Grant Line , one for each priority level. (A daisy chain is a sequence of Logic Gate s arranged in series to order events. Generally the first logic gate has first access to the grant. The daisy chain order established the order of the devices at that priority level.) In the case of the PDP-11 design, this meant that the interrupt grant order was determined by how close the physical hardware was to the CPU on the bus. When the CPU responded, the device would place its vector address on the bus; this was the address of a 4-byte block of memory. The CPU would then load the Status Register and program counter from the vector table; the new contents of the status register would generally temporarily disable interrupts. The address in the program counter would be the starting address of the code to run for the interrupt. The interrupt code would then service the device, and in the process, write to the interrupting device to re-enable the interrupt signal. Finally, a special RTI (return from interrupt) instruction would return the CPU to where it was before the interrupt (which might have been in a lower-priority interrupt). Note that this process prevents loss of interrupts; at every stage, if the interrupt is not serviced, it remains in place, to be sensed on the next cycle. If a sequence were erroneously started (as from a defective device controller), the CPU would time out, generating a special spurious interrupt; the spurious interrupt would warn users of bad hardware. Higher performance members of the PDP-11 family, starting with the PDP-11/45 , departed from the single bus approach. Instead, memory was handled by dedicated circuitry and space in the CPU cabinet, while the Unibus continued to be used for I/O only. In the PDP-11/70 this was taken a step further, with the addition of a dedicated interface from disks and tapes, via the Massbus to memory. Designed for mass production Finally, the PDP-11 was designed to be produced in a factory by semiskilled labor. All of the dimensions of its pieces were relatively non-critical. It used a Wire-wrapped Backplane . That is, the Printed Circuit Board plugged into a backplane connector. The backplane connector had terminals that could be connected to by wrapping wires around them. The terminal would cut the insulation around the wire and bite into the wire to form a gas-tight (i.e. corrosion-proof, therefore reliable) connection. The connector blocks were very similar to Telephone Connection Blocks . THE LSI-11 The LSI-11 (PDP-11/03) was the first PDP-11 model produced using Large-scale Integration ; the entire CPU was contained on 4 LSI chips made by Western Digital (the MCP-1600 chip set). It used a bus which was a close variant of the Unibus called the Q-Bus ; it differed from the Unibus primarily in that addresses and data were multiplexed onto a shared set of wires, as opposed to having separate sets of wires, as in the Unibus. It also differed slightly in how it addressed I/O devices and it eventually allowed a 22-bit physical address (whereas the Unibus only allowed an 18-bit physical address) and block-mode operations for significantly improved bandwidth (which the Unibus did not support). The CPU's Microcode includes a debugger that directly communicated to a standard serial RS-232 or Current Loop terminal. This was useful because the microcode is the part of the irreducible guts of the computer, a critical part of the Control Unit . If it doesn't work, there is no computer. The debugger provided a way to examine the computer's registers, memory and input and output devices. Thus, if the CPU worked at all, it was possible to examine and correct the computer's internal state. The built-in debugger avoided the expense and inconvenience of a front panel with an array of switches and lights, which was then the typical way to enter digital data into a near-dead computer. These two innovations meant that most of the time, the computer just worked. If it did not boot from its big disk, it would boot from its floppy. If the hardware worked at all, it talked to you through a terminal in a familiar way. Later Q-Bus based systems such as the 11/23 series and 11/73,83 series were based upon chip sets designed in house by Digital Equipment Corporation. Of interest, the Q-Bus PDP-11/83 and Unibus PDP-11/84 shared the same CPU and memory circuit boards. The PDP-11/84 having a Unibus adapter. There were significant other innovations in the Q-Bus lineup. A system variant of the PDP-11/03 introduced full system Power On Self Test (POST) and the 11/83 introduced a primitive (by today's standards) anticipatory CPU cache pre-load as well as a high speed private memory interconnect (buss). On later model Q-Bus based systems (such as the PDP-11/73B), microcode also included a memory map and diagnostic utility, and an array of Bootstrap programs with which all DEC disk drives were compatible. (This is not to be confused with bootstrap ROM, a feature found on many PDP-11s, often in form of a separate board, which was mapped into the physical address space). An early publication of programming language. THE DECLINE OF THE PDP-11 The basic design was extremely good, and was continually updated to use newer technologies. Ultimately, however, the 16-bit architecture proved to be a limitation which could not be overcome by tweaks and add-ons. While some models could support larger physical address spaces using memory mapping hardware, all programs were restricted to a 16-bit Virtual Address Space with only 64K bytes of memory. When inexpensive VLSI Memory chips became available in the 1980s, PDP-11 software was not capable of using large amounts of memory easily. DEC's own successor to the PDP-11, the VAX-11 (for "Virtual Address Extension (to the PDP-11)") addressed all of these issues, but was initially aimed at the high-end time sharing market. The early VAXes contained a PDP-11 compatibility mode, so could be considered PDP-11s by application programmers. As engineers migrated to architectures that supported a larger address space, 32-bit computing began to be supported on Microprocessor chips such as the Motorola 68000 and Intel 80386 processors and their successors; eventually the economics of large-scale production of those chips eliminated any cost advantage for the PDP-11. A line of personal computers based on the PDP-11, the DEC Professional series, failed, along with two other DEC PC offerings. DEC discontinued the final PDP-11 models in 1997. The PDP-11 design and operating system licenses were finally sold to Mentec , Inc., an Irish producer of LSI-11 based boards for Q-Bus and ISA architecture personal computers. By the late 1990s, not only DEC but most of the New England computer industry which was built around minicomputers like the PDP-11 also collapsed in the face of microcomputer-based UNIX and Windows servers. ARCHITECTURAL DETAILS The following information is found in DEC's PDP-11 Processor Handbook (see Gordon Bell's 1969 edition ). General register addressing modes (R is a general register, 0 to 7; (R) is the contents of that register.) :0. Register - the value is to or from a register: OPR R ; R contains operand :1. Register deferred - register is used as a memory address to read or write: OPR (R) ; R contains address :2. Autoincrement: OPR (R)+ ; R contains address, then increment (R) :3. Autoincrement deferred: OPR @(R)+ ; R contains address of address, then increment (R) by 2 :4. Autodecrement: OPR -(R) ; Decrement (R), R contains address :5. Autodecrement deferred: OPR @-(R) ; Decrement (R) by 2, then R contains address of address :6. Index: OPR X(R) ; (R)+X is address, second word of instruction :7. Index deferred: OPR @X(R) ; (R)+X is address (second word) of address Program counter addressing modes The program counter (PC) can also be used as a general purpose register, providing the following effectively additional addressing modes, using the mechanisms of the addressing modes above: :2. Immediate: OPR #N ; Operand is contained in the instruction :3. Absolute: OPR @#A ; Absolute address is contained in the instruction :6. Relative: OPR A ; PC+2+X is address. PC+2 is updated PC :7. Relative deferred: OPR @A ; PC+2+X is address of address. PC+2 is updated PC Memory management Some PDP-11 processors included memory management to support virtual addressing. The physical address space was extended to 18 or 22 bits, though the logical address space remained limited to 16 bits. Additionally, in some models, beginning with 11/45, the usable address space was doubled by instruction/data space separation. Some operating systems, notably Unix since edition V7, and RSX11-M+, relied on this feature. PDP-11 instruction repertoire The PDP-11 possesses a powerful instruction repertoire. Single Operand instructions One part of the word specifies the operation, referred to as "opcode" (short for "operation code", the second part provides information for locating the operand.
Double Operand instructions the first part of the word specifies the operation to be performed, the remaining two parts provide information for locating the operands.
Program Control instructions The first part of the word specifies the operation to be performed, the second part indicates where the action is to take place in the program.
Jump & Subroutine instructions
Miscellaneous instructions
Condition Code operations
The four condition codes in the processor status word (PSW) are
"Extended Instruction Set" (EIS) The EIS was an option for 11/35/40 and 11/03, and was standard on newer processors.
"Floating Instruction Set" (FIS) The FIS instruction set was an option for the PDP-11/35/40 and 11/03
"Floating Point Processor" (FPP) This was the optional floating point processor option for 11/45 and most subsequent models.
"Commercial Instruction Set" (CIS) The CIS microcode option for 11/23/24, add-in modules for the 11/44, and one version of the 11/74. ASSEMBLY LANGUAGE PROGRAMMING EXAMPLE used for PDP-11]] A complete " Hello, World! " program in PDP-11 macro assembler, to run under RT-11 : .TITLE HELLO WORLD .MCALL .TTYOUT,.EXIT HELLO:: MOV #MSG,R1 ;STARTING ADDRESS OF STRING 1$: MOVB (R1)+,R0 ;FETCH NEXT CHARACTER BEQ DONE ;IF ZERO, EXIT LOOP .TTYOUT ;OTHERWISE PRINT IT BR 1$ ;REPEAT LOOP DONE: .EXIT MSG: .ASCIZ /Hello, world!/ .END HELLO If this file is HELLO.MAC, the RT-11 commands to assemble, link and run (with console output shown) are as follows: .MACRO HELLO ERRORS DETECTED: 0 .LINK HELLO .R HELLO Hello, world! . (The RT-11 command prompt is ".") For a more complicated example of MACRO-11 code, two examples chosen at random are Kevin Murrell's KPUN.MAC , or Farba Research's JULIAN routine. More extensive libraries of PDP-11 code can be found in the Metalab freeware and Trailing Edge archives. PDP-11 MODELS The PDP-11 processors tended to fall into several natural groups depending on the original design upon which they are based and which I/O bus they used. Within each group, most models were offered in two versions, one intended for OEMs and one intended for end-users. Unibus models The following models used the Unibus as their principal bus:
Q-bus models The following models used the Q-Bus as their principal bus:
Models without standard bus
The PDT series were desktop systems marketed as "smart terminals". The /110 and /130 were housed in a VT100 terminal enclosure. The /150 was housed in a table-top unit which included two 8" floppy drives, 3 asynchronous serial ports, 1 printer port, 1 modem port and 1 synchronous serial port and required an external terminal. All three employed the same chipset as used on the LSI-11/03 and LSI-11/2 in four "microm"s. There was an option which combined two of the microms into one dual carrier, freeing one socket for an EIS/FIS chip.
The DEC Professional series were desktop PCs intended to compete with IBM's earlier 8088 and 80286 based personal computers. The models were equipped with 5 1/4" floppy disk drives and hard disks, except the 325 which had no hard disk. The original operating system was P/OS, which was essentially RSX-11M+ with a menu system on top. As the design was intended to avoid software exchange with existing PDP-11 models, their ill fate in the market was no surprise for anyone except DEC. RT-11 was eventually ported to the PRO series. A port to the PRO for RSTS/E was also done internal to DEC, but was not released. The PRO-325 and -350 units were based on the DCF-11 ("Fonz") chipset, the same as found in the 11/23, 11/23+ and 11/24. The PRO-380 was based on the DCJ-11 ("Jaws") chipset, the same as found in the 11/53,73,83 and others, though running only at 10 MHz because of limitations in the support chipset. Models that were planned but never introduced
Special purpose versions ]]
Clandestine clones The PDP-11 was sufficiently popular that several unauthorized clones were produced behind the Iron Curtain . At least some of these were pin-compatible with DEC's PDP-11s and could share peripherals and system software. These include:
OPERATING SYSTEMS Several Operating System s were available for the PDP-11 From Digital: From third parties:
SEE ALSO EXTERNAL LINKS
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