Information AboutJtag |
| CATEGORIES ABOUT JOINT TEST ACTION GROUP | |
| ieee standards | |
| electronics manufacturing | |
| embedded systems | |
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JTAG was an industry group formed in 1985 to develop a method to test populated circuit boards after manufacture. At the time, multi-layer boards and non-lead-frame , a supplement that contains a description of the Boundary Scan Description Language (BSDL) was added. Since then, this standard has been adopted by Electronics companies all over the world. Boundary-scan is nowadays mostly synonymous with JTAG. While designed for printed circuit boards, JTAG is nowadays primarily used for accessing sub-blocks of Integrated Circuit s, and is also useful as a mechanism for Debugging Embedded System s, providing a convenient "back door" into the system. When used as a debugging tool, an In-circuit Emulator - which in turn uses JTAG as the transport mechanism - enables a programmer to access an on-chip Debug module which is integrated into the CPU , via the JTAG interface. The debug module enables the programmer to debug the software of an Embedded System . In most ICs today, all internal registers are on one of many scan chains. This allows all Combinatorial Logic to be tested completely even while an IC is in the circuit card and possibly while in a functioning system. When combined with BIST , the JTAG scan chain enables a low overhead, completely embedded solution to testing an IC for certain static faults (shorts, opens, and logic errors). The scan chain mechanism does not generally help diagnose or test for Timing , temperature or other dynamic operational errors that may occur. ELECTRICAL CHARACTERISTICS A JTAG interface is a special four/five-pin interface added to a chip, designed so that multiple chips on a board can have their JTAG lines Daisy-chain ed together, and a Test Probe need only connect to a single "JTAG port" to have access to all chips on a Circuit Board . The connector pins are #TDI (Test Data In) #TDO (Test Data Out) #TCK (Test Clock) #TMS (Test Mode Select) #TRST (Test Reset) optional. Test reset signal is not shown in the image. Since only one data line is available, the protocol is necessarily Serial like SPI . The clock input is at the TCK pin. Configuration is performed by manipulating a State Machine one bit at a time through a TMS pin. One bit of data is transferred in and out per TCK clock pulse at the TDI and TDO pins, respectively. Different instruction modes can be loaded to read the chip ID, sample input pins, drive (or float) output pins, manipulate chip functions, or bypass (pipe TDI to TDO to logically shorten chains of multiple chips). The operating frequency of TCK varies depending on the chip, but it is typically 10-100 MHz (100-10 ns per bit). When performing boundary scan on integrated circuits, the signals manipulated are between different functional blocks of the chip, rather than between different chips. The TRST pin is an optional active-low reset to the test logic - usually asynchronous, but sometimes synchronous, depending on the chip. If the pin is not available, the test logic can be reset by clocking in a reset instruction synchronously. Data presented to TDI must be valid for some chip-specific ''Setup'' time before and ''Hold'' time after the rising edge of TCK. TDO data is valid for some chip-specific time after the falling edge of TCK. This can be seen e.g. with the JTAG timing diagram of the DS4550 chip (http://pdfserv.maxim-ic.com/en/ds/DS4550.pdf). Even though few consumer products provide an explicit JTAG port connector, the connections are very often available on the Printed Circuit Board as a remnant from development Prototyping . When exploited, these connections often provide an excellent means for Reverse Engineering . TEST PINS During testing, I/O signals enter and leave the chip through the boundary-scan cells. The boundary-scan cells can be configured to support external testing for interconnection between chips or internal testing for logic within the chip. To provide the boundary scan capability, IC vendors add additional logic to each of their devices, including scan registers for each of the signal pins, a dedicated scan path connecting these registers, four or five additional pins, and control circuitry. The overhead for this additional logic is minimal and generally well worth the price to have efficient testing at the board level. COMMON EXTENSIONS Manufacturer's extensions: COP, ARM ETM (Embedded Trace Macrocell), OnCE etc. WIDESPREAD USES
CLIENT SOFTWARE The JTAG interface is accessed using some JTAG-enabled application. Free software
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