Information AboutJhdl |
| CATEGORIES ABOUT JHDL | |
| hardware description languages | |
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When the design is ready to be placed in a fabric, the developer simply generates an EDIF netlist and imports it into his favorite toolkit. Once imported, the developer should be able to transfer the circuit via a JTAG cable. EDIF netlisting is supported for the XC4000, Virtex, and Virtex-II series of FPGA s. JHDL was developed at BYU in the Configurable Computing Laboratory , the project initiated in 1997 {Link without Title} . FEATURES The JHDL language features include:
Behavioral synthesis is not yet fully supported. The integrated JHDL Workbench environment is designed to allow developers to graphically test and trace their circuit designs. This tool includes:
NAMING Originally, the J in "JHDL" stood for "Java". However, to prevent trademark issues, the name has been Backronym ed to stand for Just-Another '''H'''ardware '''D'''escription '''L'''anguage. EXTERNAL LINKS |
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