Information AboutCray T3e |
| CATEGORIES ABOUT CRAY T3E | |
| supercomputers | |
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The Cray T3E was Cray Research 's second-generation Massively Parallel supercomputer architecture, launched in 1995. Like the previous Cray T3D It was a fully distributed memory machine using a 3D Torus topology interconnection network. The T3E initially used the DEC Alpha 21164 (EV5) Microprocessor and was designed to scale from 8 to 2176 ''Processing Elements'' (PEs). Each PE had between 64 MB and 2 GB of DRAM and a 6-way interconnect router with a payload bandwidth of 480 MB/s in each direction. Unlike many other MPP systems, including the T3D, the T3E was fully self-hosted and ran the UNICOS /mk Distributed Operating System with a ''GigaRing'' I/O subsystem integrated into the torus for network, disk and tape I/O. The original T3E (retrospectively known as the T3E-600) had a 300 MHz processor clock. Later variants, using the faster 21164A (EV56) processor, comprised the '''T3E-900''' (450 MHz), '''T3E-1200''' (600 MHz), '''T3E-1200E''' (with improved memory and interconnect performance) and '''T3E-1350''' (675 MHz). The T3E was available in both air-cooled (''AC'') and liquid-cooled (''LC'') configurations. AC systems were available with 16 to 128 user PEs, LC systems with 64 to 2048 user PEs. A 1480-processor T3E-1200 was the first supercomputer to achieve a performance of more than 1 Teraflops running a Computational Science application, in 1998 {Link without Title} . EXTERNAL LINKS
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