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| electronic design automation | |
The cost of such a failure is very high, and includes Photomask costs, engineering costs, and Opportunity Cost due to delayed product introduction. Therefore Electronic Design Automation tools have been developed to analyze, prevent, and correct these problems. History In the early days of VLSI design, digital chip circuit design and layout were manual processes. The use of abstraction and the application of Automatic Synthesis Techniques have since allowed designers to express their designs using High-level Languages and apply an Automated Design Process to create very complex designs, ignoring the electrical characteristics of the underlying circuits to a large degree. However, scaling trends (see Moore's Law ) brought electrical effects back to the forefront in recent technology nodes. With scaling of technology below 0.25 µm, the wire delays have become comparable or even greater than the gate delays. As a result the wire delays needed to be considered to achieve timing closure. In nanometer technologies at 0.13 µm and below, unintended interactions between signals (or noise) became an important consideration for digital design. At these technology nodes, the performance and correctness of a design cannot be assured without considering noise effects. Overview In analog circuits, designers are concerned with noise that arise from physical sources, such as Thermal Noise , Flicker Noise , and Shot Noise . These noise sources on the one hand present a lower limit to the smallest signal that can be amplified, and on the other, define an upper limit to the useful amplification. In digital circuits, noise arises not from fundamental physical sources, but from the operation of the circuit itself, primarily the switching of other signals. Higher interconnect density has led to each net having neighbors that are closer, thus leading to increased coupling capacitance between neighboring nets. As process shrink as a consequence of Moore's Law , several effects have conspired to make noise problems worse:
These effects have increased the interactions between signals and decreased the noise immunity of digital CMOS circuits. This has led to noise being a significant problem for digital ICs that must be considered by every digital chip designer prior to Tape-out . Finding Signal Integrity Problems Typically, a designer would take the following steps for his verification:
Modern signal integrity tools perform all these steps automatically, producing reports that give a design a clean bill of health, or a list of problems that must be fixed. Fixing Signal Integrity Problems Once a problem is found, it must be fixed. Typical fixes include:
Each of these fixes may possibly cause other problems. This type of issue must be addressed as part of Design Flows and Design Closure . REFERENCES
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