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HISTORY AND CHARACTERISTICS The concept of reconfigurable computing has been around since the 1960s, when Gerald Estrin 's landmark paper proposed the concept of a computer consisting of a standard processor and an array of “reconfigurable” hardware. The main processor would control the behavior of the reconfigurable hardware. The reconfigurable hardware would then be tailored to perform a specific task, such as image processing or pattern matching, as quickly as a dedicated piece of hardware. Once the task was done, the hardware could be adjusted to do some other task. This resulted in a hybrid computer structure combining the flexibility of software with the speed of hardware; unfortunately this idea was way ahead of its time in terms of electronic technology. In the last decade there was a renaissance in this area of research with many proposed reconfigurable architectures developed both in industry and academia such as, Matrix, Garp, Elixent, XPP, Silicon Hive, Montium, Pleiades, Morphosys, PiCoGA. Such designs were feasible due to the relentless progress of silicon technology that allowed complex designs to be implemented on a single chip. The world's first commercial reconfigurable computer, the Algotronix CHS2X4, was completed in 1991. It was not a commercial success, but it was promising enough that Xilinx Inc. (the inventor of the Field-Programmable Gate Array (FPGA) ) purchased the technology and hired the Algotronix staff {Link without Title} . Currently there are a number of vendors with commercially available reconfigurable computers aimed at the has developed a family of reconfigurable computers based on their IMPLICIT+EXPLICIT architecture and MAP processor. All of the offerings are hybrid "Estrin" computers with traditional microprocessors coupled to user-programmable FPGAs. The systems can be used as traditional cluster computers without using the FPGAs (in fact, the FPGAs are an option on the XD1 and the SGI RASC). The XD1 and SGI FPGA reconfiguration is accomplished either via the traditional Hardware Description Languages (HDL) or using a high level languages like the graphical tool Starbridge Viva or C -like languages like for example Handel-C from Celoxica , Impulse-C from Impulse Accelerated Technologies or Mitrion-C from Mitrionics . According to the XD1 progamming guide, "Development of the raw FPGA logic file is a complex process that requires specialized knowledge and tools." SRC has developed a ''"Carte"'' compiler takes existing high-level languages like C or Fortran , and with a few modifications, compiles them for execution on both the FPGA and microprocessor. According to SRC literature, "...application algorithms are written in a high-level language such as C or Fortran. Carte extracts the maximum parallelism from the code and generates pipelined hardware logic that is instantiated in the MAP. It also generates all the required interface code to manage the movement of data to and from the MAP and to coordinate the microprocessor with the logic running in the MAP." (note that SRC also allows a traditional HDL flow to be used). The XD1 communicates between microprocessor and FPGA over its RapidArray interconnection network. The SRC systems communicate via the SNAP memory interface, and/or the (optional) Hi-Bar switch. Clearly, classifications of reconfigurable architectures are still being developed and refined as new architectures are developed; no unifying taxonomy has been suggested to date. However, several recurring parameters can be used to classify these systems. GRANULARITY The granularity of the reconfigurable logic is defined as the size of the smallest functional unit ( CLB ) that is addressed by the mapping tools. Low granularity, which can also be known as fine-grained, often implies a greater flexibility when implementing algorithms into the hardware. However, there is a penalty associated with this in terms of increased power, area and delay due to greater quantity of routing required per computation. Fine-grained architectures work at the bit-level manipulation level; whilst coarse grained processing elements ( RDPU ) are better optimised for standard data path applications. One of the drawbacks of coarse grained architectures are that they tend to lose some of their utilisation and performance if they need to perform smaller computations than their granularity provides, for example for a one bit add on a four bit wide functional unit would waste three bits. This problem can be solved by having a coarse grain array ( RDPA ) and a FPGA on the same chip. Coarse-grained architectures ( RDPA ) are intended for the implementation for algorithms needing word-width data paths ( RDPU ). As their functional blocks are optimized for large computations they will perform these operations more quickly and power efficiently than a smaller set of functional units connected together with some interconnect, this is due to the connecting wires are shorter, meaning less wire capacitance and hence faster and lower power designs. The consequence of having larger computational blocks is that when the size of operands may not match the algorithm, thereby causing an inefficient utilisation of resources. Often the type of applications to be run are known in advance allowing the logic, memory and routing resources to be tailored (for instance, see KressArray Xplorer ) to enhance the performance of the device whilst still providing a certain level of flexibility for future adaptation. Examples of this are domain specific arrays aimed at gaining better performance in terms of power, area, throughput than their more generic finer grained FPGA cousins by reducing their flexibility. RATE OF RECONFIGURATION Configuration of these reconfigurable systems can happen at deployment time, between execution phases or during execution. In a typical reconfigurable system, a bit stream is used to program the device at deployment time. Fine grained systems by their own nature requires greater configuration time than more coarse-grained architectures due to more elements needing to be addressed and programmed. Therefore more coarse-grained architectures gain from potential lower energy requirements, as less information is transferred and utilised. Intuitively, the slower the rate of reconfiguration the smaller the energy consumption as the associated energy cost of reconfiguration are amortised over a longer period of time. Partial reconfiguration aims to allow part of the device to be reprogrammed while another part is still performing active computation. Partial reconfiguration allows smaller reconfigurable bit streams thus not wasting energy on transmitting redundant information in the bit stream. Compression of the bit stream is possible but careful analysis is to be carried out to insure that the energy saved by using smaller bit streams is not outweighed by the computation needed to decompress the data. HOST COUPLING Often the reconfigurable array is used as a processing accelerator attached to a host processor. The level of coupling determines the type of data transfers, latency, power, throughput and overheads involved when utilising the reconfigurable logic. Some of the most intuitive designs use a peripheral bus to provide a coprocessor like arrangement for the reconfigurable array. However, there have also been implementations where the reconfigurable fabric is much closer to the processor, some are even implemented into the data path, utilising the processor registers. The job of the host processor is able to perform the control functions, configure the logic, schedule data and to provide external interfacing. ROUTING/INTERCONNECTS The flexibility in reconfigurable devices mainly comes from their routing interconnect. One style of interconnect made popular by FPGA s vendors, Xilinx and Altera are the island style layout, where blocks are arranged in an array with vertical and horizontal routing. A layout with inadequate routing may suffer from poor flexibility and resource utilisation, therefore provides limited performance. If too much interconnect is provide this requires more transistors than necessary, consuming more silicon area, longer wires and having more power consumption. TOOL FLOW Generally, tools for configurable computing systems can be split up in two parts, CAD tools for reconfigurable array and compilation tools for CPU. The front-end compiler is an integrated tool, and will generate a structural hardware representation that is input of hardware design flow. Hardware design flow for reconfigurable architecture can be classified by the approach adopted by three main stages of design process: technology mapping, placement algorithm and routing algorithm. The software frameworks differ in the level of the programming language. Some types of reconfigurable computers are microcoded processors where the Microcode is stored in RAM or EEPROM , and changeable on Reboot or on the fly. This could be done with the AMD 2900 series Bit Slice Processor s (on reboot) and later with FPGA s (on the fly). Some Dataflow processors are implemented using reconfigurable computing. TERMINOLOGY REFERENCES G. Estrin, "Organization of Computer Systems—The Fixed Plus Variable Structure Computer," ''Proc. Western Joint Computer Conf.'', Western Joint Computer Conference, New York, 1960, pp. 33-40. EXTERNAL LINKS
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