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An ISA includes a specification of the set of all binary codes ( Opcode s) that are the native form of commands implemented by a particular CPU Design . The set of opcodes for a particular ISA is also known as the Machine Language for the ISA.

"Instruction set architecture" is sometimes used to distinguish this set of characteristics from the Microarchitecture , which is the set of processor design techniques used to implement the instruction set (including Microcode , Pipelining , Cache systems, and so forth). Computers with different Microarchitecture s can share a common instruction set. For example, the Intel Pentium and the AMD Athlon implement nearly identical versions of the X86 instruction set, but have radically different internal designs.

This concept can be extended to unique ISAs like TIMI (Technology-Independent Machine Interface) present in the IBM System/38 and IBM AS/400 . TIMI is an ISA that is implemented as low-level software and functionally resembles what is now referred to as a Virtual Machine . It was designed to increase the longevity of the platform and applications written for it, allowing the entire platform to be moved to very different hardware without having to modify any software except that which comprises TIMI itself. This allowed IBM to move the AS/400 platform from an older CISC architecture to the newer POWER architecture without having to rewrite any parts of the OS or software associated with it.


INSTRUCTION SET DESIGN

When designing microarchitectures, engineers use Register Transfer Language (RTL) to define the operation of each instruction of an ISA.
Historically there have been 4 ways to store that description inside the CPU :
  • all early computer designers, and some of the simpler later RISC computer designers, hard-wired the instruction set.

  • Many CPU designers compiled the instruction set to a Microcode ROM inside the CPU. (such as the Western Digital MCP-1600 )

  • Some CPU designers compiled the instruction set to a writable ).


An ISA can also be Emulate d in software by a Interpreter . Due to the additional translation needed for the emulation, this is usually slower than directly running programs on the hardware implementing that ISA. Today, it is common practice for vendors of new ISAs or microarchitectures to make software emulators available to software developers before the hardware implementation is ready.

Some instruction set designers choose the "0xff" all-ones instruction (and the "00" all-zeros instruction) to be some kind of software interrupt

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Fast virtual machines are much easier to implement if an instruction set meets the
Popek And Goldberg Virtualization Requirements .

On systems with multiple processors, Non-blocking Synchronization algorithms are much easier to implement if the instruction set includes support for something like "fetch-and-increment" or "load linked/store conditional (LL/SC)" or "atomic Compare And Swap ".


Code density

In early computers, progam memory was expensive and limited, and minimizing the size of a program in memory was important.
Thus the '' Code Density '' -- the combined size of the instructions needed for a particular task -- was an important characteristic of an instruction set. Instruction sets with high code density employ powerful instructions that can implicity perform several functions at once. Typical complex instruction-set computers ( CISC ) have instructions that combine one or two basic operations (such as "add", "multiply", or "call subroutine") with implicit instructions for accessing memory, incrementing registers upon use, or dereferencing locations stored in memory or registers. Some software-implemented instruction sets have even more complex and powerful instructions.

Reduced instruction-set computers ( RISC ), first widely implement during a period of rapidly-growing memory subsystems, traded off simpler and faster instruction-set implementations for lower code density (that is, more program memory space to implement a given task). RISC instructions typically implemented only a single explicit instruction, such as an "add" of two registers or the "load" of a memory location into a register.



Instruction sets may be categroized by the number of operands in their most comppex instructions:
  • 0-operand ("zero address machines") -- these are also called Stack Machine s, and all operations take place using the top one or two positions on the stack. Adding two numbers here can be done with three instructions: push ''a'', push ''b'', '''add''', '''pop''' ''c'';

  • 1-operand -- this model was common in early computers, and each instruction performs its operation using a single operand and places its result in a single Accumulator register: load ''a'', '''add''' ''b'', '''store''' ''c'';

  • 2-operand -- most RISC machines fall into this category, though many CISC machines also fall here as well. For a RISC machine (requiring explicit memory loads), the instructions would be: load ''a,reg1'', load ''b,reg2'', '''add''' ''reg1,reg2'', '''store''' ''reg2'';

  • 3-operand -- some CISC machines, and a few RISC machines fall into this category. The above example here might be performed in a single instruction in a machine with memory operands: add ''a,b,c'', or more typically (most machines permit a maximum of two memory operations even in three-operand instructions): '''move''' ''a,reg1'', add ''reg1,b,c''. In three-operand RISC machines, all three operands are typically registers, so explicit load/store instructions are needed. An instruction set with 32 registers requires 15 bits to encode three register operands, so this scheme is typically limited to instructions sets with 32-bit instructions or longer;

  • more operands -- some CISC machine permit a varity of addressing modes that allow more than 3 register-based operands for memory accesses.


There has been research into Executable Compression as a mechanism for improving code density. The mathematics of Kolmogorov Complexity describes the challenges and limits of this.


LIST OF ISAS

This list is far from comprehensive as old architectures are abandoned and new ones invented on a continual basis. There are many commercially available Microprocessor s and Microcontroller s implementing ISAs in all shapes and sizes. Customised ISAs are also quite common in some applications, e.g. ARC International , Application-specific Integrated Circuit ,
FPGA , and Reconfigurable Computing . Also see History Of Computing Hardware .


ISAs commonly implemented in hardware



ISAs commonly implemented in software with hardware incarnations



ISAs never implemented in hardware



SEE ALSO


Categories of ISA



Examples of commercially available ISA



Others



EXTERNAL LINKS