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Functional verification is very difficult - it is equivalent to Program Verification , and is NP-hard or even worse - and no solution has been found that works well in all cases. However, it can be attacked by many methods. None of them are perfect, but each can be helpful in certain circumstances:
  • Logic Simulation simulates the logic before it is built.

  • Simulation acceleration applies special purpose hardware to the logic simulation problem.

  • Emulation builds a version of system using programmable logic. This is expensive, and still much slower than the real hardware, but orders of magnitude faster than simulation. It can be used, for example, to boot the operating system on a processor.

  • Formal Verification attempts to prove mathematically that certain requirements (also expressed formally) are met, or that certain undesired behaviors (such as deadlock) cannot occur.

  • HDL-specific versions of Lint , and other heuristics, are used to find common problems.


Simulation based verification is widely used to "simulate" the design. Each line in HDL is exercised as stimulus is provided. A test-bench is built to functionally verify the design by providing meaningful scenarios to check that given certain input, the design performs to specification.

Different coverage metrics are defined to assess that the design has been adequately exercised. These include function coverage (has every function been exercised?), statement coverage (has each line of HDL been exercised?), and branch coverage (has each direction of every branch been exercised?). None of these are sufficient to prove a design works, but all are helpful in pointing out areas of the HDL that have not been tested.