Esterel Studio

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Esterel

Information About

Esterel Studio

FEATURES

Rigorous executable specifications.

Unlimited hierarchical design and synthesis flow.

Support of signed / unsigned integers of arbitrary size or arithmetic with no bit loss.

Generated VHDL, Verilog, C, C++, SystemC all share the same exact behavior.

Powerful sequential control and preemption primitives.

Co-simulation with all HDL simulators.

Automatic detection of potential data overflow.

Automatic VHDL and C testbench generation.

Formal verification of properties and assertions.

ECO support and critical path displays.