The microprocessor is directly connected to DRAM memory through an integrated memory controller.
The microprocessor is directly connected through a natively implemented HyperTransport to a high performance I/O subsystem.
The microprocessor is directly connected to other CPUs through a proprietary extension running on top of two additional natively implemented HyperTransport interfaces allowing support of a cache-coherent Non-Uniform Memory Access multi-CPU memory access protocol and Symmetric Multiprocessing .
