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Design Rules Design Rules are a series of parameters provided by Semiconductor Manufacturer s that enable the designer to verify the correctness of his or her Schematic and/or Mask Set . Design rules are specific to a particular semiconductor manufacturing process. A design rule set specifies certain geometric and connectivity restrictions to ensure sufficient margins to account for variability in semiconductor manufacturing processes, so as to ensure that most of the parts work correctly. Academic design rules are often specified in terms of a scalable parameter, λ, so that all geometric tolerances in a design may be defined as integer multiples of λ. This simplifies the migration of existing chip layouts to newer processes. Industrial rules are more highly optimized, and only approximate uniform scaling. Design rule sets have become increasingly more complex with each subsequent generation of semiconductor process. Design Rule Checking Software The main objective of design rule checking (DRC) is to achieve a high overall yield and reliability for the design. If design rules are violated the design may not be functional. To meet this goal of improving die yields, DRC has evolved from simple measurement and Boolean checks, to more involved rules that modify existing features, insert new features, and check the entire design for process limitations such as layer density. A completed layout consists not only of the geometric representation of the design, but also data that provide support for manufacture of the design. While design rule checks do not validate that the design will operate correctly, they are constructed to verify that the structure meets the process constraints for a given design type and process technology. DRC software usually takes as input a layout in the GDSII standard format, and produces a report of design rule violations that the designer may or may not choose to correct. Carefully "stretching" or waiving certain design rules is often used to increase performance and component density at the expense of yield. Most DRC products define some Language to describe the operations needed to be performed in DRC. For e.g Mentor Graphics uses Standard Verification Rule Format (SVRF) language in their DRC decks. A deck is a set of DRC rules. DRC is a very computationally intense task. If run on a single CPU, customers may have to wait up to a week to get the result of a Design Rule check for modern designs. Most design companies require DRC to run in less than a day to achieve reasonable cycle times since the DRC will likely be run several times prior to design completion. With today's processing power, full-chip DRC's may run in much shorter times as quick as one hour depending on the chip complexity and size. Some example of DRC's in IC design include: active to active spacing well to well spacing minimum channel length of the transistor minimum metal width metal to metal spacing metal fill density (for processes using CMP) ESD and I/O rules Commercial DRC Software Major products in the ''DRC'' area of ''EDA'' are:
All these companies are working on versions that run on many CPUs, to dramatically reduce the elapsed time required. Estimated annual sales of ''DRC'' software are in the $200 to $300 million range. The cost of a single site license of semiconductor EDA software, including DRC components, may exceed $1 million. REFERENCES
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