| Branch Target Predictor |
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| CATEGORIES ABOUT BRANCH TARGET PREDICTOR | |
| instruction processing | |
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Branch target prediction is not the same as Branch Prediction . Branch prediction attempts to guess whether the branch will be taken or not. In more parallel processor designs, as the instruction cache latency grows longer and the fetch width grows wider, branch target extraction becomes a bottleneck. The recurrence is:
In machines where this recurrence takes two cycles, the machine loses one full cycle of fetch after every predicted taken branch. As predicted branches happen every 10 instructions or so, this can force a substantial drop in fetch bandwidth. Some machines with longer instruction cache latencies would have an even larger loss. To ameliorate the loss, some machines implement branch target prediction: given the address of a branch, they predict the target of that branch. A refinement of the idea predicts the start of a sequential run of instructions given the address of the start of the previous sequential run of instructions. This predictor reduces the recurrence above to:
As the predictor RAM can be 5-10% of the size of the instruction cache, the fetch happens much faster than the instruction cache fetch, and so this recurrence is much faster. If it were not fast enough, it could be parallelized, by predicting target addresses of target branches. EXTERNAL LINKS # The Power 5 paper describes a modern branch target prediction system |
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