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PRINCIPLE DMA is an essential feature of all modern computers, as it allows devices to transfer data without subjecting the CPU to a heavy load. Otherwise, the CPU would have to copy each piece of data from the source to the destination. This is typically slower than copying normal blocks of memory since access to I/O devices over a peripheral bus is generally slower than normal system RAM. During this time the CPU would be unavailable for other tasks. A DMA transfer essentially copies a block of memory from one device to another. While the CPU initiates the transfer, it does not execute the transfer itself. For so-called "third party" DMA, as is normally used with the ISA bus, the transfer is performed by a DMA controller which is typically part of the motherboard chipset. More advanced bus designs such as PCI typically use bus-mastering DMA, where the device takes control of the bus and performs the transfer itself. A typical usage of DMA is copying a block of memory from system RAM to or from a buffer on the device. Such an operation does not stall the processor, which as a result can be scheduled to perform other tasks. DMA transfers are essential to high performance Embedded System s. It is also essential in providing so-called Zero-copy implementations of peripheral Device Driver s as well as functionalities such as network packet routing, audio playback and streaming video. EXAMPLES ISA For example,a PC's ISA DMA controller has 16 DMA channels of which 7 are available for use by the PC's CPU. Each DMA channel has associated with it a 16-bit address register and a 16-bit count register. To initiate a data transfer the device driver sets up the DMA channel's address and count registers together with the direction of the data transfer, read or write. It then instructs the DMA hardware to begin the transfer. When the transfer is complete the device then interrupts the CPU. "Scatter-gather" DMA allows the transfer of data to multiple memory areas in a single DMA transaction. It is equivalent to the chaining together of multiple simple DMA requests. Again, the motivation is to off-load multiple I/O interrupt and data copy tasks from the CPU. DRQ stands for DMA request; DACK for DMA acknowledge. These symbols are generally seen on hardware Schematic s of computer systems with DMA functionality. They represent electronic signalling lines between the CPU and DMA controller. SEE ALSO EXTERNAL LINKS
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