Turion 64

Turion 64 is AMD 's 64- Bit mobile Processor , intended to compete with Intel 's '' Pentium M ''. It is compatible with AMD's Socket 754 and is equipped with 512 or 1024 KiB of L2 cache, a 64-bit single channel on-die memory controller, and an 800MHz HyperTransport bus. Battery saving features, like '' PowerNow! '' ('' Cool'n'Quiet ''), are central to the marketing and usefulness of the CPU. A new socket for Turion 64 and other mobile AMD processors, known as Socket S1 , is scheduled to arrive in 2006 .

MODEL NUMBER METHODOLOGY

The model numbers may make it hard for anyone to compare one Turion with another Turion, or even an Athlon 64. The model name is two letters followed by two numbers. The first two numbers together designate a processor class, while the digits represent a PR Rating . The closer the second letter is to ''Z'', the greater it is designed for mobility as measured by power consumption. Take for instance, an MT-30 and an ML-34. Since the T in the MT-30 is closer to Z than the L in ML-34, it means the MT-30 consumes less power, and therefore, more mobility, than the ML-34. But since 34 is greater than 30, the ML-34 is faster than the MT-30.

AMD TURION 64 X2

The AMD Turion 64 X2 is the dual core variant of the Turions, intended to compete with the Intel Core Duo. It is planned to be released on May 9, 2006. It will debut on Socket S1 , and will feature the usage of DDR2 memory. It will also include more power-saving features. There will be seven models initially-

25W TDP:

MT-36: 1.6 GHz, 512 KiB (x2) L2 cache

MT-38: 1.6 GHz, 1024 KiB (x2) L2 cache

MT-40: 1.8 GHz, 512 KiB (x2) L2 cache

MT-42: 1.8 GHz, 1024 KiB (x2) L2 cache

35W TDP:

ML-44: 2.0 GHz, 512 KiB (x2) L2 cache

ML-46: 2.0 GHz, 1024 KiB (x2) L2 cache

ML-48: 2.2 GHz, 1024 KiB (x2) L2 cache

(the model numbers may not be correct, see {Link without Title} )

AMD Turion 64 X2 will first appear on IBM 's 90nm Silicon On Insulator (SOI) process, but will migrate to 65nm, likely with Silicon-Germanium ( SiGe ) stressed process which was recently achieved through the combined effort of IBM and AMD , with 40% improvement over comparable 65nm processes.

CORES

Lancaster (90 nm SOI)

L1 cache: 64 + 64 KiB (data + instructions)

L2 cache: 512 or 1024 KiB, fullspeed

MMX , Extended 3DNow! , SSE , SSE2 , SSE3 , AMD64 , PowerNow! , NX Bit

Socket 754 , HyperTransport (800 MHz, HT800)

VCore: 1.00V - 1.45V

Power consumption ( TDP ): 25/35 Watt max

First release: March 10 , 2005

Clock rate: 1600, 1800, 2000, 2200, 2400 MHz

--- 25W TDP :

-- MT-28: 1600 MHz (512 KiB L2-Cache)

-- MT-30: 1600 MHz (1024 KiB L2-Cache)

-- MT-32: 1800 MHz (512 KiB L2-Cache)

-- MT-34: 1800 MHz (1024 KiB L2-Cache)

-- MT-37: 2000 MHz (1024 KiB L2-Cache)

-- MT-40: 2200 MHz (1024 KiB L2-Cache)

--- 35W TDP :

-- ML-28: 1600 MHz (512 KiB L2-Cache)

-- ML-30: 1600 MHz (1024 KiB L2-Cache)

-- ML-32: 1800 MHz (512 KiB L2-Cache)

-- ML-34: 1800 MHz (1024 KiB L2-Cache)

-- ML-37: 2000 MHz (1024 KiB L2-Cache)

-- ML-40: 2200 MHz (1024 KiB L2-Cache)

-- ML-42: 2400 MHz (512 KiB L2-Cache)

-- ML-44: 2400 MHz (1024 KiB L2-Cache)

	CATEGORIES ABOUT TURION 64

	advanced micro devices products

	x86 microprocessors

	amd 886

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Turion 64