Information AboutSystemc |
| CATEGORIES ABOUT SYSTEMC | |
| hardware description languages | |
| hardware verification languages | |
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The behaviours (processes) defined may be instantiated any number of times, and provisions are made for processes defined by hierarchies of other processes, as one would expect. The language thus offered has semantical similarities to VHDL and Verilog , but may be said to have a syntactical overhead compared to these. On the other hand, greater freedom of expressiveness is offered in return, like Object Oriented Design Partitioning , template classes and Dynamic Memory Allocation . Which is more: SystemC is ''both'' a description language ''and'' a simulation kernel. The code written will compile together with the library's simulation kernel to give an executable that behaves like the described model when it is run. The performance of this simulation kernel is not to be compared with that of commercial VHDL/Verilog simulators at the present. LANGUAGE FEATURES Modules Modules are the basic building blocks of a SystemC design hierarchy. A SystemC model usually consists of several modules which communicate via ports. Ports Ports allow communication from inside a module to the outside (usually to other modules) Processes Processes are the main computation elements. They are concurrent. Channels Channels are the communication element of SystemC. They can be either simple wires or complex communication mechanisms like fifo's or bus channels. Elementary Channels:
Interfaces Ports use interfaces to communicate with channels. Events Allow the synchronisation between processes. Data types SystemC introduces several data types which support the modeling of hardware. Extended standard types:
Logic types:
Fixed point types:
EXAMPLE Example code of an adder:
EXTERNAL LINKS Further information about this open-source project can be found at SystemC homepage . |
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