Information AboutItanium 2 |
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The Itanium 2 is the successor of the first Itanium processor and is an IA-64 architecture Microprocessor . It was developed jointly by Hewlett-Packard (HP) and Intel , and introduced on July 8 , 2002 . The Itanium 2 processor architecture is based on a derivative of VLIW , dubbed Explicitly Parallel Instruction Computing (EPIC). It is theoretically capable of performing roughly 8 times more work per clock cycle than other CISC and RISC architectures due to its Parallel Computing Microarchitecture (see Parallel Computing ), however performance is heavily dependent on compilers and their ability to generate code which efficiently utilizes the available units of the processor. The Itanium 2 has seen heavy use in compute-bound Super Computer s, and large corporate database servers, where massive Parallelism and compile-time optimizations are most effective. All Itanium 2 processors to date share a common cache hierarchy. They have 16 KiB of Level 1 instruction cache and 16 KiB of Level 1 data cache. The L2 cache is unified (both instruction and data) and is 256 KiB. The Level 3 cache is also unified and varies in size from 1.5 MiB to 9 MiB. In an interesting design choice, the L2 cache contains sufficient logic to handle semaphore operations without disturbing the main ALU. (The upcoming Montecito , however, will feature a split L2 cache, adding a dedicated 1MiB L2 cache for instructions and thereby effectively growing the original 256 KiB L2 cache, which becomes a dedicated data cache.) The Itanium 2 bus is occasionally referred to as the Scalability Port, but much more frequently as the McKinley bus. It is a 200 MHz, 128-bit wide, Double Pumped bus capable of 6.4 GB/s — more than three times the bandwidth of the Merced bus. In 2004, Intel released processors with a 266 MHz bus, increasing bandwidth to 8.5 GB/s. In early 2005, processors with a 10.6 GB/s, 333 MHz bus were released. Most systems sold by enterprise server vendors that contain 4 or more processor sockets use proprietary Non-uniform Memory Access architectures (NUMA) that supersede the more limited front side bus of 1 and 2 CPU socket servers. REVISIONS McKinley McKinley was the first version of Itanium 2, manufactured in an 180 nm process. It was released at speeds of 900 MHz and 1 GHz, with cache sizes of 1.5 MiB and 3 MiB. It added hardware support for the branchlong instruction of the IA-64 instruction set. IA-32 performance, while improved, was still much slower than that of current x86 processors; McKinley's x86 performance was similar to that of a Pentium II at 2/3 the clock speed. Madison Madison was initially introduced on s. On September 8 , 2003 , a 1.4 GHz version with 1.5 MiB of cache was released. 1.4 GHz and 1.6 GHz versions with 3 MiB of cache were launched on April 13 , 2004 . November 8 , 2004 saw the release of the first processor in the Madison 9M series, at 1.6 GHz with 9 MiB of cache. On July 18 , 2005 , more variations of the Madison 9M were introduced, including 1.67 GHz models with a 333 MHz FSB and either 6 MiB or 9 MiB of cache. On introduction, the latter part set a record SPEC fp result of 2,801 in a Hitachi, Ltd. Computing Blade . In January 2005 OpenVMS was added to the line up of Operating Systems able to run on these processors. Hondo Hondo was announced as the HP mx2 dual-processor module on February 18 , 2003 and started shipping in early 2004. It consists of two Madison cores with 32 MiB of L4 cache and fits in the same space as a normal Itanium 2 CPU. It is only available from HP. Currently the cores run at 1.1 GHz with 4 MiB L3 cache each. OpenVMS for Itanium is able to use the MX2 variant. Deerfield Deerfield was released on September 8 , 2003 . With 1.5 MiB of cache, running at 1 GHz, this was the first low voltage Itanium processor. Its 62 watt power envelope made it more suited for blade and 1U servers. Fanwood The Fanwood core debuted on November 8 , 2004 . Versions include a 1.6 GHz edition with 3 MiB of L3 cache with either 200 MHz or 266 MHz FSB and a low voltage 1.3 GHz version with 3 MiB L3 cache at 200 MHz. UPCOMING REVISIONS The future of the Itanium family apparently lies in multi-core chips, as the available information about coming generations like ''Montecito'', ''Montvale'', and ''Tukwila'' shows. (Those are internal code names; the final products will most likely also bear the Itanium brand, possibly as ''Itanium 3'' or perhaps just ''Itanium 2''.). Montecito See Also: Montecito (processor) Montecito will be the first Itanium processor to have two cores per die. It was originally planned to feature advanced power and thermal management improvements. However, it has already been announced that the ''Foxton'' dynamic clock speed feature will be removed due to quality concerns. Montvale See Also: Montvale (processor) Montvale will cover a Montecito on-steroids. Earlier data suggested that Montvale's clock speed would have likely hit 2.5-2.6 GHz, sitting on a 400 MHz FSB. Tukwila See Also: Tukwila (processor) Tukwila, the first 65 nm design, due in 2008. Tukwila will consist of at least 4 cores, with each core being multithreaded. Notably, it is likely to feature a new bus called Common System Interface . Ultimately, CSI is intended to provide socket compatibility with Xeon processors; however, as of October 2005, the CSI roadmap for Xeon processors has been delayed until at least 2009. Poulson See Also: Poulson (processor) Few details are known, other than the existence of the codename. EXTERNAL LINKS |
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