Information AboutIbm 1620 |
| CATEGORIES ABOUT IBM 1620 | |
| ibm hardware | |
| 1620 | |
| early computers | |
| mainframe computers | |
THE 1620'S ARCHITECTURE It was a variable " Word " length decimal ( BCD ) computer with a memory that could hold anything from 20,000 to 60,000 decimal digits increasing in 20,000 decimal digit increments. While the 5-digit addresses could have addressed 100,000 decimal digits, no machine larger than 60,000 decimal digits was ever built. Memory was accessed two decimal digits at the same time (even-odd digit pair for numeric data or one '' Alphameric '' character for text data). Each decimal digit was 6 bits, composed of an odd parity Check bit, a '''F'''lag bit, and four BCD bits for the value of the digit in the following format: C F 8 4 2 1 The Flag bit had several uses:
In addition to the valid BCD digit values there were three ''special'' digit values (these could NOT be used in calculations): C F 8 4 2 1 1 0 1 0 - Record Mark (right most end of record) 1 1 0 0 - Numeric Blank (blank for punched card output formatting) 1 1 1 1 - Group Mark (right most end of a group of records for disk I/O) Instructions were fixed length (12 decimal digits), consisting of a 2-digit " Op Code ", a 5-digit "P Address", and a 5-digit "Q Address". Fixed-point data "words" could be any size from two decimal digits up to all of memory not used for other purposes. Floating-point data "words" (using the hardware floating point option) could be any size from 4 decimal digits up to 102 decimal digits (2 to 100 digits for the mantissa and 2 digits for the exponent). The machine had no programmer-accessible registers: all operations were memory to memory (including the Index Register s of the 1620 II ). Character and Op codes The table below lists Alphameric mode Characters (and Op codes). The table below lists Numeric mode Characters. A flawed architecture Although the IBM 1620's architecture was very popular in the scientific and engineering community, computer scientist Edsger Dijkstra pointed out several flaws in its design in EWD37, "A review of the IBM 1620 data processing system" (see http://www.cs.utexas.edu/users/EWD/index00xx.html at the Dijkstra archive at the University of Texas). Dijkstra pointed out flaws including the fact that the 1620's Branch and Transmit instruction together with Branch Back allow a grand total of ONE level of nested subroutine call, forcing the programmer of any code with more than one level to decide where the use of this "feature" would be most effective. He also showed how the paper tape reading support of the 1620 could not properly read paper tapes with record marks on them, since record marks were used to terminate the characters read in storage (one effect of this, although he did not mention it, is that the 1620 ''cannot'' duplicate a tape with record marks: when punching a tape and the first record mark that was read in is encountered, the punch instruction punches an EOL on the tape instead and stops punching!). Most 1620 installations used the more-convenient punch card input/output, when it became available, rather than paper tape. The successor to the 1620, the IBM 1130 was based on a totally different, 16-bit binary architecture. SOFTWARE IBM supplied the following software for the 1620:
HARDWARE IMPLEMENTATION Most of the logic circuitry of the 1620 was a type of logic levels of ''SDTRL'' circuits (''C Level'') were: high – 1V, low – -1V. Relay circuits used either of two logic levels (''T Level'') were: high – 51V to 46V, low – 16V to 0V or (''W Level'') were: high – 24V, low – 0V. These circuits were constructed of individual discrete components mounted on single sided paper-epoxy Printed Circuit boards 2.5 by 4.5 inches (38 by 114 mm) with a 16 pin Gold plated edge connector, that IBM referred to as ''SMS'' cards ('' Standard Modular System ''). The amount of logic on one card was similar to that in one 7400 Series SSI or simpler MSI package (e.g., 3 to 5 logic gates or a couple of flip-flops). These boards were inserted in sockets on racks, that IBM referred to as ''gates''. The machine had the following "gates" in its basic configuration:
There were two different types of Core Memory used in the 1620:
The address decoding logic of the Main memory also used two planes of 100 Pulse Transformer cores per module to generate the X-Y Line half-current pulses. There were two models of the 1620, each having totally different hardware implementations: DEVELOPMENT HISTORY In 1958 IBM assembled a team at the Poughkeepsie, New York development laboratory to study the "small scientific market". Initially the team consisted of Wayne Winger (Manager), Robert C. Jackson, and William H. Rhodes. The competing computers in this market were the Librascope LGP-30 and the Bendix G-15 , both were Drum Memory machines and it was concluded that IBM could offer nothing really new in that area. To compete effectively would require use of technologies that IBM had developed for larger computers, yet the machine would have to be produced at the least possible cost. To meet this objective, the team set the following requirements:
The internal code name CADET was selected for the machine. One of the developers says that this stood for "'''C'''omputer with '''AD'''vanced '''E'''conomic '''T'''echnology", however others recall it as simply being one half of ''"SPACE - CADET"'', where '''SPACE''' was the internal code name of the IBM 1401 machine, also then under development. The team expanded with the addition of Anne Deckman, Kelly B. Day, William Florac, and James Brenza. They completed the CADET prototype in the spring of 1959. Meanwhile the San Jose, California facility was working on a proposal of its own. IBM could only build one of the two and the Poughkeepsie proposal won because "the San Jose version is top of the line and not expandable, while your proposal has all kinds of expansion capability - never offer a machine that cannot be expanded". Management was not entirely convinced that core memory could be made to work in small machines, so Gerry Ottaway was loaned to the team to design a drum memory as a backup. During acceptance testing by the Product Test Lab repeated core memory failures were encountered and it looked likely that management's predictions would come true. However at the last minute it was found that the fan used to blow hot air through the core stack was malfunctioning, causing the core to pick up noise pulses and fail to read correctly. After the fan problem was fixed there were no further problems with the core memory and the drum memory design effort was discontinued as unnecessary.
Following announcement of the IBM 1620 on October 22 , 1959 , due to an internal reorganization of IBM, it was decided to transfer the computer from the Data Processing Division at Poughkeepsie (large scale mainframe computers only) to the General Products Division at San Jose (small computers and support products only) for manufacturing. Following transfer to San Jose, someone there jokingly suggested that the code name CADET actually stood for "'''C'''an't '''A'''dd, '''D'''oesn't '''E'''ven '''T'''ry", referring to the use of addition tables in memory rather than dedicated addition circuitry. This stuck and became very well known among the user community. Implementation "levels"
Patents
RELATED PERIPHERAL UNITS Available peripherials were:
FILM REFERENCES The '' used about a dozen scrapped 1620 front panels purchased on the surplus market, in various orientations. EXTERNAL LINKS
|
|
|