| Hypertransport |
Articles about Hypertransport |
Information AboutHypertransport |
| CATEGORIES ABOUT HYPERTRANSPORT | |
| computer buses | |
| macintosh internals | |
|
HyperTransport ('''HT'''), formerly known as '''Lightning Data Transport''' ('''LDT'''), is a bidirectional serial/parallel high-bandwidth, low-latency Computer Bus . The HyperTransport Technology Consortium is in charge of promoting and developing HyperTransport technology. The technology is used by AMD and Transmeta in X86 processors, PMC-Sierra , Broadcom , and Raza Microelectronics in MIPS microprocessors, NVIDIA , VIA , SiS , ULi/ALi , AMD , Apple Computer and HP in PC chipsets, HP , Sun Microsystems , IBM , and IWill in servers, Cray , Newisys , and PathScale in high performance computing, and Cisco Systems in routers. Notably missing from this list is semiconductor giant Intel , which continues to use a shared bus architecture. OVERVIEW HyperTransport runs at 200-1400 MHz (compared to PCI at either 33 or 66 MHz). It is also a DDR or " Double Pumped " bus, meaning it sends data on both the rising and falling edges of the Clock Signal . This allows for a maximum data rate of 2800 MTransfers/s per pair running at 1400MHz; the frequency is auto-negotiated.
HyperTransport is packet-based, with each packet always consisting of a set of 32-bit words, regardless of the physical width of the bus interconnect. The first word in a packet is always a command word. If a packet contains an address, then the last 8 bits of the command word are chained with the next 32-bit word in order to make a 40-bit address. The remaining 32-bit words in a packet are the data payload. Transfers are always padded to a multiple of 32 bits, regardless of their actual length. HyperTransport revision 1.05 contains an option allowing an additional 32-bit control packet to be prepended, when 64-bit addressing is required. HyperTransport packets enter the bus in segments known as bit times. The number of bit times that it necessitates depends on the width of the bus. HyperTransport can be used for generating system management messages, signaling interrupts, issuing probes to adjacent devices or processors, and general I/O and data transactions. There are usually two different kinds of write commands that can be used - posted and non-posted. Posted writes are ones that do not require a response from the target. This is usually used for high bandwidth devices such as UMA traffic or DMA transfers. Non-posted writes require a response from the receiver in the form of a target done. Reads also cause the receiver to generate a read response. HyperTransport also greatly facilitates power management as it readily supports C-state specific messages on various architectures. Power management messages are transmitted in system management packets, prepended with a FDF91... For specific C-state messages, the HT specification employs the use of signals like the HTStop signal. This is to allow HyperTransport controllers to disconnect end devices on the HyperTransport chain when a processor is entering a C3/C4 sleep state or other state that requires a bus disconnect. This signal is typically controlled by an end device on the HyperTransport chain that is responsible for initiating a C-state transition. Its electrical interface uses 1.2 volt Low Voltage Differential Signaling (LVDS). There has been marketing confusion between the use of HT referring to '''H'''yper'''T'''ransport and the use of HT to refer to Intel 's Hyper-Threading feature of their Pentium 4 based microprocessors. Hyper-Threading is known as '''H'''yper-'''T'''hreading '''T'''echnology ('''HTT''') or '''HT-Technology'''. Because of this potential for confusion, the HyperTransport Consortium always uses the written out form: "HyperTransport". APPLICATIONS FOR HYPERTRANSPORT Front-Side Bus Replacement The primary use for HyperTransport is to replace the Front-side Bus , which is currently different for every machine (or some set of them). For instance, a Pentium cannot be plugged into a PCI bus. In order to expand the system the front-side bus must connect through adaptors for the various standard buses, like AGP or PCI . These are typically included in the respective controller functions, namely the '' Northbridge '' and '' Southbridge ''. A similar computer implemented with HyperTransport is more flexible, as well as being faster. A single PCI<->HyperTransport adaptor chip will work with any HyperTransport enabled microprocessor and allow the use of PCI cards with these processors. The NVIDIA NForce chipset uses HyperTransport to connect its north and south bridges. Multiprocessor interconnect Another use for HyperTransport is as an interconnect for NUMA Multiprocessor computers. AMD uses HyperTransport with a proprietary Cache Coherency extension of HyperTransport as part of their Direct Connect Architecture in their Opteron and Athlon64 line of processors. The HORUS Interconnect from Newisys extends this concept to larger clusters. Router or Switch Bus Replacement
HTX A connector that is designed for HyperTransport is known as an HTX connector. HTX allows plug-in cards to be developed which support direct access to a CPU's HyperTransport interface. This connector has been used to support an ultra-low latency Message Passing interface by PathScale in their Infinipath adapter. The HyperTransport Consortium The HyperTransport Consortium is led by founding members Advanced Micro Devices (AMD), Alliance Semiconductor, Apple Computer, Broadcom Corporation, Cisco Systems, NVIDIA, PMC-Sierra, Sun Microsystems, and Transmeta. It manages the HyperTransport specification, drives new developments and promotes the consortium. As of 2005, David Rich of AMD is the President of the Consortium, Mario Cavalli is the General Manager, Brian Holden of PMC-Sierra is both the Vice President and the Chair of the Technical Working Group, and Harry Hirschman of PathScale is the Chair of the Marketing Working Group. IMPLEMENTATIONS
SEE ALSO EXTERNAL LINKS |
|
|