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the Clock Signal is used to define a time reference for the movement of data within that system. The clock distribution network distributes the clock signal(s) from a common point to all the elements that need it. Since this function is vital to the operation of a synchronous system, much attention has been given to the characteristics of these clock signals and the Electrical Network s used in their distribution. Clock signals are often regarded as simple control signals; however, these signals have some very special characteristics and attributes. CONSIDERATIONS FOR CLOCK SIGNALS Clock signals are typically loaded with the greatest Fanout , travel over the greatest distances, and operate at the highest speeds of any signal, either control or data, within the entire synchronous system. Since the data signals are provided with a temporal reference by the clock signals, the clock Waveform s must be particularly clean and sharp. Furthermore, these clock signals are particularly affected by technology scaling (see Moore's Law ), in that long global interconnect lines become significantly more resistive as line dimensions are decreased. This increased line resistance is one of the primary reasons for the increasing significance of clock distribution on synchronous performance. Finally, the control of any differences and uncertainty in the arrival times of the clock signals can severely limit the maximum performance of the entire system and create catastrophic Race Condition s in which an incorrect data signal may latch within a register. PERFORMANCE OF CLOCKED SYSTEMS Most synchronous '' Digital '' systems consist of cascaded banks of sequential Register s with Combinatorial Logic between each set of registers. The Functional Requirements of the digital system are satisfied by the logic stages. The global performance and local timing requirements are satisfied by the careful insertion of Pipeline Registers into equally spaced time windows to satisfy critical worst case '' Timing Constraints ''. The proper design of the clock distribution network ensures that these critical timing requirements are satisfied and that no race conditions exist. (See also Clock Skew .) The delay components that make up a general synchronous system are composed of the following three individual subsystems: the memory storage elements, the logic elements, and the clocking circuitry and distribution network. Interrelationships among these three subsystems of a synchronous digital system are critical to achieving maximum levels of performance and reliability. ONGOING RESEARCH Novel structures are currently under development to ameliorate these issues and provide effective solutions. Important area of research include resonant clocking techniques, on-chip optical interconnect, and local synchronization methodologies. LITERATURE The literature in this field exists in a variety of journals and conference proceedings. Examples include the IEEE Transactions of Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , the IEEE/ACM Design Automation Conference , and a host of related computer, circuits, and CAD conferences. REFERENCES
Adapted from Eby Friedman 's column in the ACM SIGDA e-newsletter by Igor Markov Original text is available at http://sigda.org/newsletter/2005/eNews_051201.html SEE ALSO |
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