| Cdc Cyber |
Article Index for Cdc |
Website Links For Cyber |
Information AboutCdc Cyber |
| CATEGORIES ABOUT CDC CYBER | |
| cdc hardware | |
| cyber | |
| supercomputers | |
Primarily aimed at large office applications instead of the traditional supercomputer tasks, some of the Cyber machines nevertheless included basic Vector Instructions for added performance in "traditional" CDC roles. CDC CYBER 170 SERIES The Cyber 170 architecture was a successor to the earlier CDC 6600 and CDC 7600 series and therefore shared many of the earlier architecture's characteristics. The central processor (CPU) and central memory (CM) operated in units of 60-bit words. In CDC lingo, the term "byte" referred to 12-bit entities (which coincided with the word size used by the peripheral processors). Characters were six bits, operation codes were six bits, and central memory addresses were 18 bits. Central processor instructions were either 15 bits or 30 bits. The 18-bit addressing inherent to the Cyber 170 series imposed a limit of 262,144 (256K) words of main memory, which was Semiconductor memory in this series. The central processor had no I/O instructions, relying upon the peripheral processor (PP) units to do I/O. A Cyber 170-series system consisted of one or two CPU s that ran at either 25 or 40 MHz, and was equipped with 10, 14 or 20 peripheral processors (PP), and up to 24 high-performance Channel Controller s for high-speed I/O . Due to the relatively slow memory reference times of the CPU (in some models, memory reference instructions were slower than a floating point divides), the CPU was normally equipped with a few words of high-speed memory used as an instruction cache. Any loop that fit into the cache (which was sometimes called ''in-stack'') would run without referencing main memory for instruction fetch. As with predecessor systems, the Cyber 170 series had eight 18-bit address registers (A0 through A7), eight operand registers (X0 through X7), and eight index registers (B0 through B7). Seven of the A registers were tied to their corresponding X register. Storing an address into register A1 through A5 caused the contents of the central memory word referenced by that address to be fetched into the corresponding X register. Likewise, storing an address into register A6 or A7 caused the contents of the corresponding X register to be stored to the central memory location referenced by the A register. The CDC Cyber 170 central processing unit consisted of multiple ''functional units'' (e.g., shift, increment, floating add) which allowed some degree of parallel execution of instructions. This parallelism allowed assembly programmers to minimize the effects of the system's slow memory fetch time by ''pre-fetching'' data from central memory well before that data was needed. By interposing independent instructions between the memory fetch instruction and the instructions manipulating the fetched operand, the time occupied by the memory fetch could be used for other computation. With this technique, coupled with the handcrafting of tight loops that fit within the instruction stack, a skilled Cyber assembly programmer could write extremely efficient code that made the most of the power of the hardware. The peripheral processor subsystem used a technique known as ''barrel and slot'' to share the execution unit; each PP had its own memory and registers, but the processor (the slot) itself executed one instruction from each PP in turn (the barrel). This is a crude form of hardware Multiprogramming . The peripheral processors had 4096 bytes of 12-bit memory words and an 18-bit accumulator register. Each PP had access to all I/O channels and all of the system's central memory (CM) in addition to the PP's own memory. The PP instruction set lacked, for example, extensive arithmetic capabilities and did not run user code; the peripheral processor subsystem's purpose was to process I/O and thereby free the more powerful central processor unit(s) to running user computations. The systems typically ran CDC's NOS (Network Operating System). Version 1 of NOS continued to be updated until about 1981; NOS version 2 was released early 1982. Besides NOS, the only other operating systems commonly used on the 170 series was '''NOS/BE''' or its predecessor '''Scope'''. These operating systems provided Time Sharing of batch and interactive applications. CDC CYBER 180 SERIES As the computing world standardized to an eight-bit byte size, CDC customers started pushing for the Cyber machines to do the same. The result was a new series of systems that could operate with either 60- or 64-bit words, although not at the same time. During the lifetime of the 170 series CDC introduced NOS/VE, which added Virtual Memory to the BE system. They considered this change so important that the newer machines able to run VE were referred to as the '''Cyber 180''' after its release. The machines were otherwise identical to the bytewise 170s. (Don't have time to formally rewrite the article, but the true 180-mode machines were microcoded processors that could and did support both instruction sets simultaneously. Their hardware was completely different from the earlier 6000/70/170 machines. The small 170-mode exchange package was mapped into the much larger 180-mode exchange package; within the 180-mode exchange package, there was a VMID -- virtual machine identifier -- that determined whether the 8/16/64-bit twos complement 180 instruction set or the 12/60-bit ones complement 170 instruction set was executed. There were 3 true 180's in the initial lineup, codenamed P1, P2, P3. P2 & P3 were larger water-cooled designs from Arden Hills. The P1 was a novel air-cooled, 60-board cabinet designed by a group in Toronto; the P1 ran on 60 Hz current (no motor-generator sets needed!). A fourth high-end 180 codenamed THETA was also under development. The 180's were initially marketed as 170/8xx machines with no mention of the new 8/64-bit system inside. However, the primary control program was a 180-mode program known as EI (Environmental Interface). The 170 operating system (NOS) utilied a single, large, fixed page within the main memory. There were a few clues that an alert user could pick up on, such as the "building page tables" message that flashed on the operator's console at startup and deadstart panels with 16 (instead of 12) toggle switches per PP word on the P2 & P3. The peripheral processors in the true 180's were always 16-bit machines with the sign bit determining whether a 16/64 bit or 12/60 bit PP instruction was being executed. The single word I/O instructions in the PP's were always 16-bit instructions, so at deadstart the PP's could set up the proper environment to run both EI plus NOS & the customer's existing 170-mode software. To hide this process from the customer, earlier in the 1980's CDC had ceased distribution of the source code for its DDS (Deadstart Diagnostic Sequence) package and turned it into the proprietary CTI (Common Tests & Initialization) package. The initial 170/800 lineup was: 170/825 (P1), 170/835 (P2), 170/855 (P3), 170/865 and 170/875. The 825 was released initially after some delay loops had been added to its microcode; it seemed the design folks in Toronto had done a little too well and it was too close to the P2 in performance. The 865 & 875 models were revamped 170/760 heads (1 or 2 processors with 6600/7600-style parallel functional units) with larger memories. The 865 used normal 170 memory; the 875 took its faster main processor memory from the Cyber 205 line. A year or two after the initial release, CDC announced the 800-series' true capabilities to its customers, and the true 180's were relabeled as the 180/825 (P1), 180/835 (P2), and 180/855 (P3). At some point the model 815 was introduced with the delayed microcode and the faster microcode was restored to the model 825. Eventually the THETA was released as the Cyber 990.) CDC CYBER 200 SERIES In 1974 CDC introduced their STAR architecture, itself a version of the 6600/7600 design with Vector Processing instructions added for high performance on math tasks. The original STAR proved to be a great disappointment when it was released, but many of its problems seemed solvable. In the late 1970s CDC finally addressed these issues and re-entered the supercomputer market with the Cyber 203, the new naming in keeping with their new branding, and perhaps to distance itself from the STAR's failure. An improved version was later released as the '''Cyber 205''', and sold fairly well. Versions were available with one to four vector pipelines, the 4-pipe version theoretically delivering 200 MFLOP in later versions, but rarely coming close on anything other than hand-written Assembly Language . Also there was a CYBER 250 which was scheduled for release in 1987 priced at $20 Million, it was later renamed the ETA30. CDC CYBERPLUS/AFP At least 21 CYBERPLUS (aka Advanced Flexible Processor, AFP) Multiprocessor installations were operational in 1986. These Parallel Processing Systems include from 1 to 256 CYBERPLUS Processors providing 250 MFLOPS each, which are connected to an existing CYBER system via a direct Memory Interconnect Architecture, this was available on NOS 2.2 CYBER 170/835, 845, 855 & 180/990 models. Each CYBERPLUS is a 16-bit processor with optional 64-bit floating point capabilities and has 256 or 512 K words of 64-bit memory. Each physical CYBERPLUS processor unit was:
Software that was bundled with the CYBERPLUS was:
One known installation was at the Gesellschaft fur Trendanalysen (GFTA) in Germany A fully configured 256 processor CYBERPLUS system would have a theoretical performance of 64 GFLOPS and weigh 256 t! |
|
|