Information About8254 |
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HISTORY In modern times, this PIT is not included as a separate chip in an x86 PC. Rather, its functionality is included as part of the motherboard's southbridge chipset. In some modern chipsets, this change may show up as measurable timing differences in accessing a PIC using the x86 I/O address space. Reads and writes to such a PIC's registers in the I/O address space may complete much faster. Newer x86 PICs include a counter through the Advanced Configuration And Power Interface ( ACPI ), a counter on the Local Advanced Programmable Interrupt Controller ( Local APIC ), and a Time Stamp Counter (TSC) introduced on the Pentium . FEATURES The timer has three counters, called channels. Each channel can be programmed to operate in one of six modes. Once programmed, the channels can perform their tasks independently. The timer is usually assigned to IRQ -0 (highest priority hardware interrupt) because of the critical function it performs and because so many devices depend on it. TYPICAL COMPONENTS Counters There are 3 Counters (or timers), which are labelled as Counter 0, '''Counter 1''' and '''Counter 2'''. Each counter has 2 input pins - '''CLK''' ( Clock input) and '''GATE''' - and 1 pin, '''OUT''', for data output. The 3 counters are 16-bit down counters independent of each other, and can be easily read by the CPU . The first counter (selected by setting D7=D6=0, see Control Word Register below) helps generate a 18.2 Hz clock Signal . The second counter (D7=0, D6=1) assists in generating timing, which will be used to refresh the DRAM memory. The last counter (D7=1, D6=0) generates tones for the PC speaker. Besides the counters, a typical Intel 8253 chipset also contains the following components: Data/Bus Buffer This block contains the logic to buffer the data bus to / from the microprocessor, and to the internal registers. It has 8 input pins, usually labelled as D7..D0, where D7 is the MSB . Read/Write Logic The Read/Write Logic block has 5 pins, which are listed below. Notice that '''X\''' denotes an active low signal.
Operation mode of the PIT is changed by setting the above hardware signals. For example, to write to the Control Word Register, one needs to set CS\=0, RD\=1, WR\=0, A1=A0=1. Control Word Register This register contains the programmed information which will be sent (by the Microprocessor ) to the device. It defines how the PIT logically works. To initialise the counters, the microprocessor must write a control word (CW) in this register. This can be done by setting proper values for the pins of the Read/Write Logic block and then by sending the control word to the '''Data/Bus Buffer''' block. The control word contains 8 bits, label D7..D0 (D7 is the MSB ).
The following table describes how to use the Read/Write bits (RW1, RW0).
Details about other bits will be provided in the next section. During a typical rountine with the PIT, the microprocessor first sends a control message, then a count message to the PIT. The counting process will start after the PIT has received these messages, and, in some cases, if it detects the Rising Edge from the GATE input signal. On most PCs, the address for Control Word Register is 043 Hex , and 040h, 041h, 042h for each counter. OPERATION MODES Operation mode is set using the D3, D2, D1 bytes of the Control Word. There are 5 modes in total. Notice that, for modes 0, 2 and 3, '''GATE''' must be set to '''HIGH''' to enable counting. For details on each mode, see the reference links. Mode 0 (D3=D2=D1=0) (Interrupt on Terminal Count) In this mode, the counter will start counting from the initial COUNT value loaded into it, down to 0. Counting rate is equal to the input clock frequency. The OUT pin is set to 0 after the '''Control Word''' is received, and counting starts one clock cycle after the '''COUNT''' message is received. OUT remains low until the counter reaches 0. Once then, OUT will be set to high until the counter is reloaded or the '''Control Word''' is written. Mode 1 (D3=D2=0, D1=1) (Hardware Trigered One Shot) The device is set up to give an output pulse that is an integer number of clock pulses, and the processed is triggered by the GATE input (hardware trigered). The output is initially low until the Control Word is written. After '''COUNT''' is written, the device will wait until the rising edge of the '''GATE''' input. One clock cycle after this Rising Edge is detected, '''OUT''' will become and remain low until the counter reaches 0. '''OUT''' will then go high, waiting for the next trigger. Mode 2 (D2=1, D1=0) (Rate Generator) In this mode, the device acts as a divide-by-n counter, which is commonly used to generate Real-time clock interrupt. Like other modes, counting process will start the next clock cycle after COUNT is sent. '''OUT''' will then remain high until the counter reaches 1, and will go low for one clock pulse. '''OUT''' will then go high again, and the whole process repeats itself. The time between the high pulses depends on the preset count in the counter's register, and is calculated using the following formula: Value to be loaded into counter = Mode 3 (D2=1, D1=1) (Square Wave Generator) This mode is similar to mode 2. However, the duration of the high and low clock pulses of the output will be different. Suppose n is the number loaded into the counter (the '''COUNT''' message), the output will be
Mode 4 (D3=1, D2=D1=0) (Software Triggered Strobe) After Control Word and '''COUNT''' is loaded, the output will remain high until the counter reaches zero. The counter will then generate a low pulse for 1 clock cyle (a strobe) - after that the output will become high again. Mode 5 (D3=1, D2=0, D1=1) (Hardware Triggered Strobe) This mode is similar to mode 4. However, the counting process is triggered by the GATE input. After receiving Control Word and '''COUNT''', the output will be set to HIGH. Once the device detects the rising edge of the '''GATE''' input, it will start counting. When the counter reaches 0, the output will go low for one clock cycle - after that it will become high again. PROGRAMMING CONSIDERATIONS On x86 PCs, many video card BIOS and system BIOS will reprogram the second counter for their own use. Reprogramming typically happens during video mode changes, when the video BIOS may be executed, and during system management mode and power saving state changes, when the system BIOS may be executed. This prevents any serious alternative uses of the timer's second counter on many x86 systems. SEE ALSO
EXTERNAL LINKS REFERENCES
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